High speed / low power server farms and server networks

ABSTRACT

A server farm has servers with at least one hybrid computing module operating at a system clock speed that optimally matches the intrinsic clock speed of a semiconductor die embedded within a high speed semiconductor chip stack or mounted upon the semiconductor carrier.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. Provisional PatentApplication No. 62/666,124, filed May 3, 2018 and incorporated herein inits entirety.

FIELD OF THE INVENTION

The present invention generally relates to the design and constructionof a server farm comprising high computational speeds and higher powerefficiency within a smaller physical footprint, wherein highercomputational speeds, smaller physical footprints, and greater powerefficiencies are generated by displacing printed circuit boards from themicroelectronic assemblies.

The present invention additional relates to power management stages thatintroduce power savings within a server farm or network of server farms.

The present invention generally relates to the design and constructionof and a regional or global network of server farms that are linkedtogether with high-speed/high power efficiency optical, wireless, andsatellite telecommunications systems.

The present invention specifically relates to server farms comprisinghybrid computing modules, further comprising high-speed semiconductorchip stacks.

The present invention specifically relates to server farm networksfurther comprising high-speed semiconductor chip stacks.

The present invention includes a solid state gyrator formed as a singlepart that is used as a lossless component of a power management stage ina server farm or is used for higher speed modulation systems within aregional or global network of server farms.

The present invention additionally relates to the use of powermanagement stages comprising resonant gate transistors and high voltagedrop inductor or transformer that transform, invert, or convertelectrical energy drawn from a power source to AC or DC voltage used byan electronic system to be managed by a single stage power managementstage or no more than two power management stages.

1. Background to the Invention

Server farms consume Mega-Watts of electrical power that strain thepower grid and drive up electrical costs to the community. Withoutsubstantial government subsidies the digital economy has notdemonstrated a real capacity to realize the strong profits. Estimatesfor the amount of power annually consumed to mine Bitcoin and othercrypto-currencies range from 15-32 Vera-Watts, costing miners 30%-60% oftheir annual revenues. These costs will only increase as the complexityof mining algorithms grows exponentially. The continued growth of thedigital economy will require adding additional capacity to the powergrid. The most economically efficient solution will reduce the powerconsumption of server farms/data centers so the additional capacity doesnot strain domestic power grids.

It is therefore desirable to introduce means by which a regional orglobal network of servers, wherein each server form has a dramaticallysmaller physical footprint and cuts its power consumption at least100-fold, thus introducing a cost structure that ensures a vibrant andprofitable digital economy thrives without government subsidies thatimpoverishes the general public.

2. Overview of the Related Art

de Rochemont U.S. Pat. No. 7,405,698 entitled “CERAMIC ANTENNA MODULEAND METHODS OF MANUFACTURE THEREOF” (the '698 application) discloses theuse of high permittivity electroceramic to form transmission lines thathave characteristic impedance that matches the input/output impedance ofa semiconductor chip, and the integration of those transmission lines onthe surface of a semiconductor die or electrical interconnect(interposer), but it does not disclose art related to transmission linesthat comprise high permittivity and high relative permeabilitydielectrics configured along the path of a transmission line that causesthe transmission line to resonate a given frequency or desired clockspeed, nor does it disclose the incorporation of passive circuits withintransmission lines in close proximity to a via within a chip stack orthe application of those devices within a server farm.

de Rochemont U.S. Pat. No. 8,715,839, filed Jun. 30, 2006, entitled“ELECTRICAL COMPONENT AND METHOD OF MANUFACTURE” (the '839 application)discloses and claims high permittivity electroceramics that by virtue ofhaving uniform nanoscale grain size and microstructure exhibitsdielectric permittivity that remains stable over standard operatingtemperatures. It also discloses the incorporation of those highpermittivity electroceramics within a capacitor that is formed on thesurface of a semiconductor die, an electrical interconnect (interposer),or within a printed circuit board, but it does not disclose itsapplication to semiconductor chip stacks or the application of thosedevices within a server form.

3. Definition of Terms

The term “average amu” is herein understood to mean the median atomicmass of a unit cell for a crystalline compound derived by summing thefractional atomic mass units contributed by elements forming the crystallattice.

The acronym “BEOL” is herein understood to be an abbreviation for BackEnd of Line and understood to mean fabrication processes that are amongthe last group of processes performed in the final assembly of asemiconductor chip.

The term “Bitcoin” is herein understood to mean a digitalcrypto-currency that is mined on a Blockchain using a computer algorithmand exists in limited supply.

The term “Blockchain” is herein understood to mean a process used toform a trusted auditable record in a digital ledger that is distributedacross a computer network.

The terms “chemical complexity”, “compositional complexity”, “chemicallycomplex”, or “compositionally complexity” are herein understood to referto a material, such as a metal or superalloy, compound semiconductor, orceramic that consists of three (3) or more elements from the periodictable.

The term “chip stack” is herein understood to mean a bonded threedimensional (3D) assembly of chips that may comprise semiconductor dieand non-semiconductor chip elements, such as sensors,micro-electromechanical systems (“MEMS”), and/or interposer circuitsthat provide passive electrical interconnections between the variouscomponents in the 3D assembly.

The term “critical performance tolerances” is herein understood to referto the ability for all passive components in an electrical circuit tohold performance values within ±1% of the desired values at alloperating temperatures over which the circuit was designed to function.

The term “distributed ledger technology” is herein understood to referto a computational platform that generates a trusted databasedistributed across a computer network wherein trust related to an entryor transaction is assured when a majority of computers that are partiesto the network confirm the entry or transaction and said entry ortransaction remains a permanent record of the computer network that canbe openly inspected and cannot be altered.

The term “electroceramic” is herein understood to refer to itsconventional meaning as being a complex ceramic material that has robustdielectric properties that augment the field densities of appliedelectrical or magnetic stimulus.

The term “integrated circuit” (or “IC”) is herein understood to mean asemiconductor chip into which a large, very large, or ultra-large numberof transistor elements have been embedded.

The term “liquid chemical deposition” (or “LCD”) is herein understood tomean a method that uses liquid precursor solutions to fabricatematerials of arbitrary compositional or chemical complexity as anamorphous laminate or free-standing body or as a crystalline laminate orfree-standing body that have atomic-scale chemical uniformity and amicrostructure that is controllable down to nanoscale dimensions.

The term “MAX-phase material” is herein understood to define achemically complex intermetallic ceramic material having the generalchemical formula M_((n+1))AX_(n), wherein M is first rowtransition-metal element, A is an “A-group” element found in columnsIII-VI of the periodic table, and X is either carbon (C) or nitrogen(N).

The term “microstructure” is herein understood to hold its traditionalmeaning of relating to the grain size, grain chemistry, and grainboundary chemistry of a polycrystalline ceramic material.

The acronym “PCB” is herein understood to reference a printed circuitboard. The term “passive component” is herein understood to refer to itsconventional definition as an element of an electrical circuit that thatmodulates the phase or amplitude of an electrical signal withoutproducing power gain.

The term “physical layer” is herein understood to understood to mean apatterned or unpatterned material layer embedded within amicroelectronic circuit wherein the material possesses some uniquephysical property that enhances the proper function of the circuit or acircuit element.

The term “resonant gate transistor” is herein understood to refer to anyof the transistor architectures disclosed in de Rochemont, U.S. Ser. No.13/216,192, “POWER FET WITH A RESONANT TRANSISTOR GATE”, wherein thetransistor switching speed is not limited by the capacitance of thetransistor gate, but operates at frequencies that cause the gatecapacitance to resonate with inductive elements embedded within the gatestructure.

The term “server farm” is herein understood to mean a large collectionof servers that functions as a data center, internet ortelecommunications switching center, or digital commerce platform usedfor high frequency trading, crytocurrency mining or exchange, a backbonefor digital banking, or a platform for eCommerce.

The term “standard operating temperatures” is herein understood to meanthe range of temperatures between −40° C. and +125° C.

The term “surface feature” is herein understood to mean one or morepatterned physical layers integrated on the surface of a substratewherein the patterns and physical properties of die physical layers aredesigned to serve some functional purpose within a microelectroniccircuit.

The term “thermoelectric effect” is herein understood to refer to itsconventional definition as the physical phenomenon wherein a temperaturedifferential applied across a material induces a voltage differentialwithin that material, and/or an applied voltage differential across thematerial induces a temperature differential within that material.

The term “thermoelectric material” is herein understood to refer to itsconventional definition as a solid material that exhibits the“thermoelectric effect”.

The term “thermomechanical” is herein understood to refer to itsconventional definition as relating to properties induced or created bythe simultaneous application of elevated temperature and mechanicalforce or pressure.

The term “thinned” is herein understood to refer to an interposer, asensor chip, or a semiconductor die that has been ground and chemicalmechanically polished to reduce its original thickness to a lesserthickness, preferably a thickness on the order of 25 μm or less.

The term “thru via” or “via” is herein understood to refer to itsconventional definition as relating to a vertical electrical connectionthat is made by filling a thru hole with an electrically conductivesubstance.

The terms “tight tolerance” or “critical tolerance” are hereinunderstood to mean a performance value, such as a capacitance,inductance, or resistance that varies less than ±1% over standardoperating temperatures.

The term “transmission line” is herein understood, for the specificpurpose of this application, to refer to any of the following: amicrostrip 352, a stripline 354, ground-cladded stripline 357,ground-cladded dielectric waveguide 355, and a dielectric slab waveguide359

The term “II-VI compound semiconductor” is herein understood to refer toits conventional meaning describing a compound semiconductor comprisingat least one element from column IIB of the periodic table including:zinc (Zn), cadmium (Cd), or mercury (Hg); and, at least one element fromcolumn VI of the periodic table consisting of: oxygen (O), sulfur (S),selenium (Se), or tellurium (Te).

The term “III-V compound semiconductor” is herein understood to refer toits conventional meaning describing a compound semiconductor comprisingat least one semi-metallic element from column III of the periodic tableincluding: boron (B), aluminum (Al), gallium (Ga), and indium (In); and,at least one gaseous or semi-metallic element from the column V of theperiodic table consisting of: nitrogen (N), phosphorous (P), arsenic(As), antimony (Sb), or bismuth (Bi).

The term “IV-IV compound semiconductor” is herein understood to refer toits conventional meaning describing a compound semiconductor comprisinga plurality of elements from column IV of the periodic table including:carbon (C), silicon (Si), germanium (Ge), tin (Sn), or lead (Pb).

The term “IV-VI compound semiconductor” is herein understood to refer toits conventional meaning describing a compound semiconductor comprisingat least one element from column IV of the periodic table including:carbon (C), silicon (Si), germanium (Ge), tin (Sn), or lead (Pb); and,at least one element from column VI of the periodic table consisting of:sulfur (S), selenium (Se), or tellurium (Te).

SUMMARY OF THE INVENTION

One embodiment of the present invention provides a server farmcomprising a server, wherein the server or servers comprise: at leastone hybrid computing module operating at a system clock speed thatoptimally matches the intrinsic clock speed of a semiconductor dieembedded within a high speed semiconductor chip stack or mounted uponthe semiconductor carrier; and one or more high-speed semiconductor chipstacks bonded to the surface of a semiconductor carrier in which atleast one passive component element, preferably all passive componentselements maintain critical performance tolerances, and have apolarization response time determined solely by orbital deformations andoperates in phase, thus does not distort, any of the applied signalcomponents forming a high-speed digital pulse operating at clock speedsup to and into the terahertz (THz) frequency domain.

The hybrid computing module within a server or plurality of servers maycomprise a power management device that further comprises a resonantgate transistor. The hybrid computing module may be configured forMinimal Instruction Set Computing by means of a chip that comprises aFORTH engine mounted on a semiconductor carrier or embedded within ahigh speed chip stack. The servers may be mounted within a plurality ofslots in 3 server rack, further comprising a harness that forms acommunications bus interface, preferably an optical interface, withother servers mounted within the server rack. The server racks may beassembled to form a server tower comprising a plurality of server racksand a harness that forms a communications bus interface, preferably anoptical interface, with other servers mourned within the server tower.The server farm may have a plurality of towers used to form at least onerow of server towers or a plurality of rows of server towers and aharness that forms a communications bus interface, preferably an opticalinterface, with other server towers distributed within a row of servertowers or between rows of server towers. The servers may be mountedwithin a plurality of slots in a server rack, further comprising aharness that forms a communications bus interface, preferably an opticalinterface, with other servers mounted within the server rack. The serverracks may be assembled to form a server tower comprising a plurality ofserver racks and a harness forms a communications bus interface,preferably an optical interface, with other servers mounted within theserver tower. The server farm may have a plurality of towers used toform at least one row of server towers or a plurality of rows of servertowers and a harness that forms a communications bus interface,preferably an optical interface, with other server towers distributedwithin a row of server towers or between rows of server towers. Theservers may be mounted within a plurality of slots in a server rack,further comprising a harness that forms a communications bus interface.preferably an optical interface, with other servers mounted within theserver rack. The server racks may be assembled to form a server towercomprising a plurality of server racks and a harness forms acommunications bus interface, preferably an optical interface, withother servers mounted within the server tower. The server farm may havea plurality of towers used to form at least one row of server lowers ora plurality of rows of server towers and a harness that forms acommunications bus interface, preferably an optical interface, withother server lowers distributed within a row of server towers or betweenrows of server towers. The hybrid computing module configured forMinimal Instruction Set Computing may utilize a computing language otherthan FORTH, but the processor chip that enables the engine to adopt aStack Machine Architecture has features similar to a FORTH engineincluding: the ability to access multiple memory spaces simultaneouslyin a single microprocessor clock cycle; and, that utilizes a minimalnumber of instruction sets through the use of separate buses to accessmemory holding the data stack, the return stack, and the program memory,among other useful program utilities. The server farm may have no needfor cache memory or predictive algorithms. The server farm may process afunction using the most efficient algorithm type (iterative, recursive,or deeply nested loop) for that specific function. The hybrid computingmodule may not have a predictive algorithm to manage the sequence ofdata or instructions sets flowing into a processor chip. The servers maybe mounted within a plurality of slots in a server rack, furthercomprising a harness that forms a communications bus interface,preferably an optical interface, with other servers mounted within theserver rack. The server racks may be assembled to form a server towercomprising a plurality of server racks and a harness forms acommunications bus interface, preferably an optical interface, withother servers mounted within the server tower. The server racks may beassembled to form a server tower comprising a plurality of server racksand a harness forms a communications bus interface, preferably anoptical interface, with other servers mounted within the server tower.The server farm may have a plurality of towers used to form at least onerow of server towers or a plurality of rows of server towers and aharness that forms a communications bus interface, preferably an opticalinterface, with other server towers distributed within a row of servertowers or between rows of server towers. The servers may be mountedwithin a plurality of slots in a server rack, further comprising aharness that forms a communications bus interface, preferably an opticalinterface, with other servers mounted within the server rack. The serverracks may be assembled to form a server tower comprising a plurality ofserver racks and a harness forms a communications bus interface,preferably an optical interface, with other servers mounted within theserver tower. The server racks may be assembled to form a server towercomprising a plurality of server racks and a harness forms acommunications bus interface, preferably an optical interface, withother servers mounted within the saver tower. The server farm may have aplurality of towers used to form at least one row of server towers or aplurality of rows of server towers and a harness that forms acommunications bus interface, preferably an optical interface, withother server towers distributed within a row of server towers or betweenrows of server towers. The server may not include a printed circuitboard.

Another embodiment of the present invention provides a server having ahybrid computing module comprising: at least one hybrid computing moduleoperating at a system clock speed that optimally matches the intrinsicclock speed of a semiconductor die embedded within a high speedsemiconductor chip stack or a semiconductor die mounted upon asemiconductor carrier, wherein at least one semiconductor embeddedwithin the high-speed semiconductor chip stack or semiconductor diemounted upon the semiconductor carrier is a resistive element X-Point(Cross-Point) memory device.

The hybrid computer module may further comprise, one or more high-speedsemiconductor chip stacks bonded to the surface of a semiconductorcarrier in which at least one passive circuit element, preferably allpassive circuit elements, consists of electroceramic dielectric membersthat maintain critical performance tolerances. The passive circuit maycomprise electroceramic dielectric members having a polarizationresponse time determined solely by orbital deformations within andoperates in phase, thus does not distort, any of the applied signalcomponents forming a high-speed digital pulse operating at clock speedsup to and into the terahertz THz) frequency domain. The electroceramicdielectric members may have high dielectric density producing a relativepermittivity (ε_(R)) in excess of ε_(R),=40, preferably in excess ofε_(R).=200. The electroceramic dielectric members may have highdielectric density producing a relative permeability (μ_(R)) in excessof μ_(R).=10, preferably in excess of μ_(R).=100. A hybrid computingmodule or high speed semiconductor chip stack may be in electricalcommunication with a power management device that further comprises aresonant gate transistor used as a power switch. The power managementdevice may be formed or mounted on the semiconductor carrier. The powermanagement device may be mounted within the harness of a server rack. Apower management device, preferably a power management device comprisinga resonant gate transistor, may convert the read voltage from aresistive memory element located at a single address location on aX-Point (Cross Point) memory system or device into a bit pulse. A powermanagement device, preferably a power management device comprising aresonant gate transistor, may simultaneously convert a plurality of readvoltages from a plurality or string of resistive memory element addresslocations within a X-Point (Cross Point) memory system of device into astring of pulsed bits or a bit string. The string of pulsed bits, or bitstring, may be produced simultaneously during a single processor clockcycle. A bit string may be interpreted as a word or a plurality ofwords. The words or plurality of words may be simultaneously input oroutput to the processor during a single clock cycle through a pluralityof independent and simultaneously operating bus interfaces managing datatraffic between memory systems/devices and processor(s), wherein thesimultaneous bus interfaces include, but are not limited to: one or moredata stack buses, one or more return stack buses, one or more registerbuses, and one or more program memory buses. A single resistive memoryelement may be used to store a plurality of addressable memory statesfrom a single memory address, and the single resistive element state isused to store a data byte or a word. A power management device,preferably a power management device comprising a resonant gatetransistor, may convert the read voltage from a resistive memory elementlocated at a single address location on a X-Point (Cross Point) memorysystem or device into a bit string that faithfully represents the databyte or word. A power management device, preferably a power managementdevice comprising a resonant gate transistor, may simultaneously converta plurality of read voltages from a plurality of resistive memoryelement address locations, each capable of storing a plurality ofaddressable memory states from a single address location within aX-Point (Cross Point) memory system or device into a plurality of databytes or words. The data bytes or words may be simultaneously producedin a single processor clock cycle.

Yet another embodiment of the present invention provides powermanagement system that delivers electrical power from the power grid ora primary electrical source to a server farm or other facility thatconsumes electrical power comprises three high efficiency powermanagement stages, preferably only requires two high efficiency powermanagement stages, between the power grid or primary power source andany internal AC or DC power bus in the server farm or any other facilitythat consumes electrical power.

The power management system may have a power efficiency of 90% thatreduces system losses to 10%, and preferably has a power efficiency of95% that reduces system losses to 5%, when delivering power from thepower grid or from a primary power source any internal AC or DC powerbus in the server farm or any other facility that consumes electricalpower. The power management system may have power efficiencies greaterthan or equal to 98%. The power management system may have AC powercomprising a hollow waveguide structure. The high efficiency powermanagement stages may comprise one or more high efficiency powermodules. The one or more power management modules may filler spurioussignals generated by Dirty Electricity from AC voltages propagatingwithin the server farm or other facility that consumes electrical power.The one or more power management modules may comprise a resonant gatetransistor. The one or more power management modules may comprise afully integrated gyrator. The one or more power management modules maycomprise a fully integrated gyrator further comprising a resonant gatetransistor. The one or more power management modules may comprise aninductor coil or transformer coils, preferably a toroidal inductor coilor transformer coils. The inductor coil or transformer coils may furthercomprise magnetic core materials. The magnetic core materials maycomprise high energy density dielectric electroceramic dielectricmembers. The power management system may have at least one inductor coilor transformer coils comprising magnetic core materials is used for anenergy storage inductor coil or within a flyback transformer. Themagnetic core materials may comprise optimal energy storage locations.The inductor coil or transformer coil windings may comprise highhardness constraining members. The high hardness constraining memberscomprise low-CTE ceramic may have a coefficient of expansion of 0.5ppm/° C. The high hardness constraining members may comprise MAX-Phasecarbide ceramic or a layered combination of low-CTE ceramic andMAX-Phase carbide ceramic. The inductor coil or transformer coils maycomprise enveloping amorphous silica dielectric located between thewindings of an inductor coil or transformer coils. The amorphous silicadielectric located between the windings may have sufficient thickness toinsulate the inductor coil and transformer coils from arc dischargeswhen the applied differential voltage drops between windings that exceed600VAC, 1 KVAC, 50 KVAC or 250 KVAC.

The high efficiency power management stage may comprises an input powerblock that may further comprise: one or more power control systems thatregulates the flow of electrical power from the power grid or a primaryelectrical source by means of current sensors and a current limiter thatelectrically isolate one or more power management modules within thepower management system, a low loss transformer stage, and one or morehigh efficiency power management modules that interface AC power inputfrom the power grid or a primary electrical power source to an AC or DCpower bus internal to the server farm or other facility that consumeselectrical power. The power control system may comprise a resonant gatetransistor. The power control system may comprise a fully integratedgyrator. The fully integrated gyrator may comprise a resonant gatetransistor. The current limiter may synchronously operate with aresonant gate transistor interfaced with a ladder circuit that rapidlymonitors changes to input currents being feed into power managementmodules to detect power spikes or pulse edges that are characteristic ofa power surge that will likely damage high efficiency power managementmodules or equipment within the server farm or other facility thatconsumes electrical power, and then uses a resonant gate transistorwithin the current limiter to shut the power surge to ground. Theresonant gate transistor may be interfaced with a ladder circuit,wherein the resonant gate transistor switches power in excess ofresonant gate transistors within the power management modules. Theresonant gate transistor may be interfaceed with a ladder circuit andmay preferably switch at speeds greater than or equal to 10× theswitching speeds of resonant gate transistors within the powermanagement modules. The power management system may comprises a fullyintegrated gyrator. The low-loss transformer stage may comprise a fullyintegrated gyrator. The one or more high efficiency power managementmodules may form a thermal interface with a thermoelectric device,preferably a thermoelectric device comprising a 3D Quantum gas. Thepower input block may form a thermal interface with a thermoelectricdevice, preferably a thermoelectric device comprise a 3D Quantum gas.

The one or more high efficiency power management modules may be AC-DCinverters when supplying DC parallel output currents to the internalpower bus. The one or more high efficiency power management modules maybe AC-AC transformers that filter dirty electricity from the AC paralleloutput currents feeding the internal power bus. The power bus mayelectrically interface with an energy storage facility. The energystorage facility may comprise a battery, a flywheel, a resonant highenergy storage device, or other means to store electrical energy.

A power management system that delivers electrical power from a primaryDC electrical source, or an AC power line on the power grid that servesa secondary customer, to a server farm or other facility that consumeselectrical power wherein, the power management system and only requirestwo (2) high efficiency power management stages, preferably onlyrequires one (1) high efficiency power management stages, between thepower grid or primary power source and any internal AC or DC power busin the server farm or any other facility that consumes electrical power.The power management system may have a power efficiency of 95% thatreduces system losses to 5%, and may preferably have a power efficiencyof 98% that reduces system losses to 2%, when delivering power from thepower grid or a primary DC electrical source or an AC power line on thepower grid that serves a secondary customer to any internal AC or DCpower bus in the server farm or any other facility that consumeselectrical power. The power management stages have power efficienciesgreater than or equal to 98%. The AC power may comprise a hollowwaveguide structure.

The high efficiency power management stages may comprise one or morehigh efficiency power modules. The one or more power management modulesmay filter spurious signals generated by Dirty Electricity from ACvoltages propagating within the server farm or other facility thatconsumes electrical power. The one or more power management modules maycomprise a resonant gate transistor. The one or more power managementmodules may comprise a fully integrated gyrator.

The one or more power management modules may comprise a fully integratedgyrator further comprising a resonant gate transistor. The one or morepower management modules may comprise an inductor coil or transformercoils, preferably a toroidal inductor coil or transformer coils. Theinductor coil or transformer coils may further comprise magnetic corematerials. The magnetic core materials may comprise high energy densitydielectric electroceramic dielectric members. The magnetic corematerials may comprise optimal energy storage locations. The powermanagement system wherein at least one inductor coil or transformercoils may comprise magnetic core materials used within an energy storageinductor coil or within flyback transformer coils. The inductor coil ortransformer coil windings may comprise high hardness constrainingmembers. The high hardness constraining members comprise low-CTE ceramichaving a coefficient of expansion of 0.5 ppm/° C.

The high hardness constraining comprise MAX-Phase carbide ceramic or alayered combination of low-CTE ceramic and MAX-Phase carbide ceramic.The inductor coil or transformer coils may comprise enveloping amorphoussilica dielectric located between the windings of an inductor coil ortransformer coils. The amorphous silica dielectric located between thewindings may sufficient thickness to insulate the inductor coil andtransformer coils from are discharges when the applied differentialvoltage drops between windings that exceed 600VAC, 1 KVAC, 50 KVAC or250 KVAC.

The power management system, wherein, a power management stage maycomprises one or more power control systems that regulates the flow ofDC electrical power a primary electrical source or AC power from a powerline serving secondary customers for the power grid by means of currentsensors and a current limiter that electrically isolate one or morepower management modules within the power management system, and mayfurther comprises one or more high efficiency power management modulesthat interface AC power input from the power grid or DC power from aprimary electrical power source to a plurality of parallel AC or DCcurrents to an equal plurality of AC or DC internal power buses withinthe server farm or other facility that consumes electrical power. Thepower control system may comprise a resonant gate transistor. The powercontrol system may comprise a fully integrated gyrator. The fullyintegrated gyrator may comprise a resonant gate transistor. The currentlimiter may synchronously operate with a resonant gate transistorinterfaced with a ladder circuit that rapidly monitors changes to inputcurrents being feed into power management modules to detect power spikesor pulse edges that are characteristic of a power surge that will likelydamage high efficiency power management modules or equipment within theserver farm or other facility that consumes electrical power, and thenuses a resonant gate transistor within the current limiter to shut thepower surge to ground. The resonant gate transistor may be interfacedwith a ladder circuit of claim 115, wherein the resonant gate transistorswitches power in excess of resonant gate transistors within the powermanagement modules. The resonant gate transistor interfaced with aladder circuit may preferably switch at speeds greater than or equal to10× the switching speeds of resonant gate transistors within the powermanagement modules. The one or more high efficiency power managementmodule may comprise a fully integrated gyrator. The one or more highefficiency power management modules may form a thermal interface with athermoelectric device, preferably a thermoelectric device comprise a 3DQuantum gas. The one or more high efficiency power management modulesmay be AC-DC inverters when the power management system is supplied withAC power from the power grid and the one or more high efficiency powermanagement modules may supply one or more DC parallel output currents tothe internal power buses. The one or more high efficiency powermanagement modules may be DC-DC converters when the power managementsystem is supplied with DC power from the primary electrical source andthe one or more high efficiency power management modules supply one ormore DC parallel output currents to one or more DC parallel outputcurrents to the internal power buses. The one or more high efficiencypower management modules may comprise AC-AC low loss transformers whenthe power management system is supplied with AC power from the powergrid and the one or more high efficiency power management modules supplyone or more AC parallel output currents to one or more internal AC powerbuses. The one or more high efficiency power management modules maysupply AC parallel output currents to a single internal AC power bus andadditional low-loss transformers may step up or step down AC voltages ona plurality of internal AC power buses.

The low-loss transformers may comprise a fully integrated gyrator. Theone or more high efficiency power management modules may compriselow-loss AC-AC transformers that filter dirty electricity from the ACparallel output currents feeding an internal power bus.

Still another embodiment of the present invention provides an inductorcoil or transformer coils that form low loss inductors and low losstransformers comprise magnetic core materials that have maximalpermeability and minimal magnetic core losses by further comprising highenergy density electroceramic members that: minimize Eddy current lossesby consisting of any one or all of the flowing atomic elements: nickel(Ni), cobalt (Co), zinc (Zn), copper (Cu) titanium (Ti), or chromium(Cr); minimize hysteresis losses by additionally consisting of any oneor all of the following atomic elements, lead (Pb), strontium (Sr) andmagnesium (Mg); minimize residual magnetic loss by additionally having amicrostructure with a uniform grain size distribution not greater than 7μm, preferably a uniform grain size distribution in the range of 5-7 μm;and further minimize Eddy current losses by embedding one or more thinamorphous silica layers having thickness ≤1 μm.

The magnetic core materials, wherein high energy density electroceramicmembers may have electrical resistivity≥10⁵ Ω-cm, preferably≥10⁷ Ω-cm.The inductor coil or transformer coils may have higher energies andhigher magnetic field strengths created by introducing dielectricdiscontinuities by include non-magnetic media within the magnetic corematerials to create “air gaps” that allow higher currents to energizethe inductor coil or transformer coils before the onset of magneticsaturation. The non-magnetic media may comprise amorphous silica. Theinductor coil transformer coils may form a closed magnetic path by meansof toroidal geometries that reduce parasitic noise generated by fringingfields and Eddy current losses generated by electromagnetic interactionsbetween magnetic fringing fields leaking out of the magnetic corematerial and currents in the coil windings. The inductor coil ortransformer coils may have a layer of non-magnetic material insertedbetween a coil winding and a high energy density electroceramic memberwithin the magnetic core materials to minimize fringing fieldspenetrating into conductive elements of a winding. The inductor coil ortransformer coils, wherein the high energy density electroceramicmembers may have relative permeability μ_(R)≥20, preferably μ_(R)≥400.The inductor coil or transformer coils, wherein dielectricdiscontinuities may be placed at optimal energy storage locations withinthe magnetic core material to optimize performance as an energy storinginductor coil or a flyback transformer. The inductor coil or transformercoils, wherein the optimal energy storage location within the magneticcore material of a flyback transformer may be beneath one or moresecondary coil windings and the optimal energy storage location withinthe magnetic core material of an energy storing inductor may be beneathone or more the coil winding. The energy storing inductor or flybacktransformer coil, wherein dielectric discontinuities within optimalenergy storage locations may comprise a continuous volume of ultra-lowloss amorphous silica dielectric or a collection of small volumedistributed amorphous silica dielectric members. The optimal energystorage locations may optimally comprise a patterned three dimensionalarray of dielectric discontinuities that generates a stable distributionof localized micro-volumes of extreme magnetic flux densities thatinduce maximal inductive coupling within the adjacent windings as theenergy storing inductor coil or flyback transformer is reverse cycled,wherein physical spacing between said of micro-volumes of extrememagnetic flux density may range between 1/10,000th to 1/10th the volumeof the magnetic core material located beneath the secondary coilwinding. The energy storing inductor or flyback transformer coil,wherein the maximal volume of the patterned three dimensional array ofdielectric discontinuities within optimal energy storage locations maycomprise 1.2× the width of winding above the optimal energy storagelocation multiplied by the cross-sectional area of the magnetic corematerial around which the winding is wrapped. The energy storinginductor or flyback transformer coil, wherein the minimal volume of thepatterned three dimensional array of dielectric discontinuities withinoptimal energy storage locations may comprise the width or less than thewidth of the of winding above the optimal energy storage locationmultiplied by the cross-sectional area of the magnetic core materialaround winch the winding is wrapped. The inductor coil or transformercoils, wherein coil windings may be encapsulated with envelopingamorphous silica dielectric to enable the inductor coil or transformercoils to sustain very large differential voltage drops. The inductorcoil or transformer coils, wherein high hardness constraining membersmay be located at the center of a coil winding and the high hardnessconstraining members may be enveloped by low resistivity conductingelements having resistivity less than 10⁻⁵ Ω-cm, preferably withresistivity less than 10⁻⁷ Ω-cm.

The inductor coil or transformer coils, wherein the constraining membersmay comprise low-CTE ceramic having a coefficient of 0.5 ppm/° C. Theconstraining members may additionally comprise MAX-Phase ceramic inlayered combination with the low-CTE ceramic. The inductor coil ortransformer coils may comprise toroidal geometry that forms a magneticcurrent having a closed path to minimize spurious noise. The inductorcoil or transformer coils, wherein proximity losses and flux jumpinglosses may be reduced by maintaining consistent spacing between coilwindings. The transformer coils, wherein interleaved primary andsecondary coil windings may be used to effectuate turn ratios. Thetransformer coils, wherein interleaved primary and secondary coilwindings may include one or more parallel groupings of windings formedthrough parallel connection to ring conductor that electrical connectsthe parallel groupings in series, while the windings of the othertransformer coil is electrically connected in series.

Even another embodiment of the present invention provides a magneticcore material that stores magnetic energy and reduces magneticsaturation, wherein the magnetic core material comprises dielectricdiscontinuities embedded within high energy density electroceramicmembers that: minimize Eddy current losses by consisting of any one orall of the flowing atomic elements: nickel (Ni), cobalt (Co), zinc (Zn),copper (Cu) titanium (Ti), or chromium (Cr); minimize hysteresis lossesby additionally consisting of any one or all of the following atomicelements: lead (Pb), strontium (Sr) and magnesium (Mg); and minimizeresidual magnetic loss by additionally having a microstructure with auniform grain size distribution not greater than 7 μm, preferably auniform grain size distribution in the range of 5-7 μm.

The dielectric discontinuities may comprise amorphous silica dielectric.The magnetic core materials may have high energy density electroceramicmembers have electrical resistivity≥10⁵ Ω-cm, preferably≥10⁷ Ω-cm. Themagnetic core material may minimize Eddy current losses by embedding oneor more thin amorphous silica layers having thickness≤1 μm within themagnetic core material. The high energy density electroceramic membersmay have relative permeability μ_(R)≥20, preferably μ_(R)400. Themagnetic core material may have dielectric discontinuities placed atoptimal energy storage locations within the magnetic core material tooptimize performance as a magnetic energy storage medium within amagnetic circuit. The dielectric discontinuities within optimal energystorage locations may comprise a continuous volume of ultra-low lessamorphous silica dielectric. The dielectric discontinuities withinoptimal energy storage locations may comprise a collection ofmicro-volumes of amorphous silica dielectric discontinuities rather thana continuous volume. The collection of micro-volume dielectricdiscontinuities may optimally comprise a patterned three dimensionalarray of micro-volume dielectric discontinuities that generate a stabledistribution of localized micro-volumes of extreme magnetic fluxdensities that induce maximal inductive coupling with conductiveelements of the magnetic circuit when it is reverse cycled.

The magnetic circuit may be flyback transformer coils and the optimalenergy storage locations within the magnetic core material of a flybacktransformer may be beneath one or more secondary coil windings. Themagnetic circuit may be an energy storing inductor coil and the optimalenergy storage locations within the magnetic core material may bebeneath one or more the coil windings.

A further embodiment of the present invention provides a fullyintegrated gyrator that comprises a high speed stack of semiconductordevices wherein one of the stacked semiconductor devices comprisestransistor elements needed to form an operational amplifier and at leastone of those transistor elements further is a resonant gate transistor.

The transistor elements may be resonant gate transistors. Thesemiconductor devices may be diced chips. The semiconductor devices maycomprise semiconductor wafers. The fully integrated gyrator may have anoperational amplifier formed by forming a bonded electrical interfacethrough an internal major surface with a semiconductor interposer devicethat comprises all of the passive circuit elements needed to form acomplete operational amplifier circuit using the two stackedsemiconductor devices as a bonded stacked pair. The semiconductorinterposer device may comprise all of the passive circuit elementsneeded to form a complete gyrator circuit comprising the two stackedsemiconductor devices. The passive circuit elements may comprise highenergy density electroceramic members that operate to criticalperformance tolerances. The high, energy density electroceramic membersmay possess a microstructure that has uniform gram chemistry and grainsize that restricts dielectric polarization to orbital deformationshaving femto-second response times.

The circuit input may be on an external major surface of onesemiconductor device and the circuit output is on the external majorsurface of the paired semiconductor interposer device. The fullyintegrated gyrator may operate as a loss-less transformer. A fullyintegrated gyrator may invert a network filter embedded within thesemiconductor interposer device. A high speed stack of semiconductordevices may comprise a plurality of coupled bonded-pair devices whereinat least one bonded pair in the stack is a fully integrated gyrator. Ahigh speed stack of semiconductor devices may have a plurality of fullyintegrated gyrators bonded into the high speed stack of semiconductordevices in series with the output of one flowing to the input of theother to form a cascading circuit. The cascading circuit may be a lowloss transformer. The cascading circuit may operate in tandem to form acomplex circuit comprising at least gyrator as a low-loss inductortransformer and one or more gyrators a filter or a network filter. Thefully integrated gyrator may have passive circuit elements integratedwithin the semiconductor interposer device and positioned at or in closeproximity to a via connection to the paired semiconductor device formingthe gyrator. The folly integrated gyrator may have a resonant gatetransistor that comprises a high resistivity transistor element,imparting resistance between greater than 1 KΩ, preferably greater than1MΩ, between the gate and source electrodes The rally integrated gyratormay have a resonant gate transistor that comprises a plurality passiveelement integrated within the gate electrode to induce resonance over awide frequency hand or at particular frequency bands that optimizegain-bandwidth of the resonant gate transistor that improves thefunction of the fully integrated gyrator. The fully integrated gyratormay functions as a lossless transformer, The lossless transformer may beassembled within a cascading stack of fully integrated gyrators. Thelossless transformer may be assembled as a parallel array of cascadingstack of rally integrated gyrators.

An even further embodiment of a present invention provides a regionaland global network of server farms and telecommunications modes,consisting of microelectronic hardware functioning as routing, dataprocessing, and relays at telecommunications nodes throughout thenetwork that further comprise, a high-speed semiconductor chip slack,hybrid computing modules, or both, circuits wherein capacitive passivecircuit elements exclusively comprise electroceramic dielectric membershaving nanoscale microfracture and femto-second polarization responsetimes, resonant gate transistors, and, high efficiency power managementsystems managing digital traffic over optical, satellite and wirelesstelecommunications networks.

The hybrid computing modules may function as a FORTH engine. The highefficiency power management systems may comprise lossless transformers.The lossless transformer may comprise a fully integrated gyrator. Thetelecommunications node may further comprise a V_(DD) Modulatorcomprising a resonant gate transistor. The regional and global networkmay have telecommunications modes comprising optical, wireless, andsatellite modes.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustratively shown and described in referenceto the accompanying drawings, in which:

FIGS. 1A,1B depict a high speed semiconductor chip stack and a highspeed semiconductor chip stack mounted on a hybrid computing module.

FIGS. 2A,2B,2C depict a hybrid computing module insert as a circuit cardwithin a computing harness embedded within a server rack comprising aplurality of hybrid computing modules, wherein the server racks areinserted within a slots in a server tower, and one or more server towersare housed, preferably in sufficient numbers to form rows of servertowers within a server farm.

FIG. 3A,3B,3C,3D,3E,3F,3G depicts various embodiments and aspects of ahigh efficiency power management stage.

FIGS. 4A,4B,4C,4D,4E,4F,4G,4H,4I illustrate a fully integrated solidstate gyrator device.

FIG. 5 depicts a regional network or global network comprising serverfarms that operate at maximal computational speeds with minimal powerconsumption, as well as the use of high speed optical, wireless, orsatellite transceivers, comprising hybrid computing modules, high-speedchip stacks, fully integrated solid state gyrators, and power managementdevices at nodes within the regional or global network.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention is illustratively described above in reference tothe disclosed embodiments. Various modifications and changes may be madeto the disclosed embodiments by persons skilled in the art withoutdeparting from the scope of the present invention as defined in theappended claims.

This application incorporates by reference all matter contained in deRochemont U.S. Pat. No. 7,405,698 entitled “CERAMIC ANTENNA MODULE ANDMETHODS OF MANUFACTURE THEREOF” (the '698 application), de RochemontU.S. Pat. No. 8,715,839 filed Jun. 30, 2006, entitled “ELECTRICALCOMPONENT AND METHOD OF MANUFACTURE” (the '839 application), deRochemont U.S. Pat. No. 8,350,657 (the '657 application), filed Jan. 6,2007 entitled “POWER MANAGEMENT MODULE AND METHODS OF MANUFACTURE”, deRochemont U.S. Ser. No. 14/560,935, (the '935 application), filed Dec.4, 2014 entitled “POWER MANAGEMENT MODULE AND METHODS OF MANUFACTURE”,de Rochemont, U.S. Ser. No. 13/216,192, “POWER FET WITH A RESONANTTRANSISTOR GATE (the '192 application), de Rochemont and Kovacs, U.S.Pat. No. 8,715,814, “LIQUID CHEMICAL DEPOSITION PROCESS APPARATUS ANDEMBODIMENTS”, (the '814 application) and U.S. Pat. No. 8,354,294 (the'294 application), de Rochemont, “MONOLITHIC DC/DC POWER MANAGEMENTMODULE WITH SURFACE FET”, U.S. Pat. No. 8,552,708 (the '708application), de Rochemont, U.S. No. 8,749,054 “SEMICONDUCTOR CARRIERWITH VERTICAL POWER FET MODULE”, (the '054 application), de RochemontU.S. Pat. No. 9,023,493, “CHEMICALLY COMPLEX ABLATIVE MAX-PHASE MATERIALAND METHOD OF MANUFACTURE”, (the '493 application), de Rochemont U.S.Pat. No. 8,779,489 and U.S. Pat. No. 9,153,532, “POWER FET WITH ARESONANT TRANSISTOR GATE”, (the '489 and '532 application), de RochemontU.S. Pat. No. 9,123,768, “SEMICONDUCTOR CHIP CARRIERS WITHMONOLITHICALLY INTEGRATED QUANTUM DOT DEVICES AND METHOD OF MANUFACTURETHEREOF”, (the '768 application), de Rochemont U.S. Pat. No. 8,952,858,“FREQUENCY-SELECTIVE DIPOLE ANTENNAS”, (the '858 application), deRochemont and Kovacs U.S. Pat. No. 9,348,385, “HYBRID COMPUTING MODULE”(the '385 application), de Rochemont, “FULLY INTEGRATED THERMOELECTRICDEVICES AND THEIR APPLICATION TO AEROSPACE DE-ICING SYSTEMS”, U.S.Application No. 61/529,302 ('302), and, de Rochemont, “HIGH SPEEDSEMICONDUCTOR CHIP STACK”, U.S. Ser. No. 15/969,234 (the '234application).

The '698 application instructs on methods and embodiments that providemeta-material dielectrics, including artificial magnetic ground planes,that have dielectric inclusion(s) with performance values that remainstable as a function of operating temperature. This is achieved bycontrolling the dielectric inclusion(s)' microstructure to nanoscaledimensions less than or equal to 50 nm. de Rochemont '839 instructs theintegration of passive components that hold performance values thatremain stable with temperature in printed circuit boards, semiconductorchip packages, wafer-scale SoC die, and power management systems. deRochemont '159 instructs on how LCD is applied to form passive filteringnetworks and quarter wave transformers in radio frequency or wirelessapplications that are integrated into a printed circuit board, ceramicpackage, or semiconductor component, de Rochemont '657 instructs methodsto form an adaptive inductor coil that can be integrated into a printedcircuit board, ceramic package, or semiconductor device. de Rochemont etal. '814 discloses the liquid chemical deposition (LCD) process andapparatus used to produce macroscopically large compositionally complexmaterials, that consist of a theoretically dense network ofpolycrystalline micro-structures comprising uniformly distributed grainswith maximum dimensions less than 50 nm. Complex materials are definedto include semiconductors, metals or super alloys, and metal oxideceramics, de Rochemont '814 and '708 instruct on methods and embodimentsrelated to a fully integrated low EMI, high power density inductor coiland/or high power density power management module. de Rochemont '489 and'532 instruct on methods to integrate a field effect transistor thatswitch arbitrarily large currents at arbitrarily high speeds withminimal On-resistance into a rally integrated silicon chip carrier. deRochemont '768 instructs methods and embodiments to integratedsemiconductor layers that produce a 3-dimensional electron gas withinsemiconductor chip carriers and monolithically integratedmicroelectronic modules. de Rochemont '302 instructs methods andembodiments to optimize thermoelectric device performance by integratingchemically complex semiconductor material having nanoscalemicrostructure. de Rochemont '858 instructs means to form a circuitresonant element by folding arms of dipole antenna or transmission lineto induce inductive and capacitive loads through current vectorcoupling. de Rochemont '234 instructs means to embed one or more passivecircuit elements within or in close proximity to a via on an interposerchip or an active semiconductor chip, or an interposer chips and/oractive semiconductor chips that are embedded within a stacked assemblyof chips.

LCD methods permit the integration of high chemical complexityelectroceramics on a buried microelectronic layer with the requisitechemical precision to make the finished product economically viable. Itenables chemically complex electroceramics to be selectively depositedon a semiconductor surface at temperatures that do not damage embeddedactive circuitry. It further enables the integration of chemicallycomplex electroceramics with atomic scale chemical uniformity anduniform microstructure, including microstructure that has nanoscaleuniformity irrespective of electroceramic chemical complexity.

Reference is now made to FIGS. 1A,1B to illustrate a hybrid computermodule 1 comprising high speed semiconductor chip stacks 2 mounted uponor integrated upon a semiconductor carrier 4. The hybrid computer module1 may optionally comprise a power management device 6 mounted orintegrated upon the surface of the semiconductor carrier 4. The powermanagement device 6 may additionally comprise a resonant gate transistor8 configured as a surface or vertical FET. FIG. 1A depicts a verticalFET embedded beneath the drain electrode. The power management device 6comprising the resonant gate transistor 8, with additional art disclosedherein, enables large currents to be switched at microprocessor clockspeeds without generating significant heat. The power management device6 thus enables flow of data and instruction sets to be managed in syncwith the processor clock, thus eliminating any need for cache memorythat does not allow individual elements in cache to be individuallyaddressed. The larger number of programming stacks relegated FORTHengine architectures to embedded processor applications as the need theindustry developed greater dependencies on cache memory systems. LCDmethods enable passive circuitry that meet critical performancetolerances to be formed on the surface of metallic, dielectric, orsemiconducting substrates at process temperatures that will not alterthe diffusion profiles of any active circuitry embedded within a fullyprocessed semiconductor wafer. Passive circuitry comprising resistors,inductors, and capacitors is used to tune and filter operational signalfrequencies. The $100s of billions invested in miniaturizing transistorsare not generating great growth returns because the moment these higherspeed semiconductor chips are electrically connected to a printedcircuit board, their intrinsic clock speeds throttle down from ≥20 GHzto 2.5 GHz to 3.4 GHz. Commodity materials used to form the printedcircuit board (“PCB”) and the discrete passive circuit components thatare mounted on the PCB distort higher frequency signal components thatare needed to shape the high speed digital pulse. Therefore, means thatallow system clock speeds to optimally match the intrinsic clock speedsof the chips that comprise the system.

Printed circuit boards are required in microelectronic assembliesbecause inductors and capacitors have loose performance tolerances(typically ±10%) and do not keep their performance values stable withtemperature. As a result, these passive components are mounted on aprinted circuit board where they can be easily replaced when one or moreof them cause the system to be so far out of tune over any specifiedoperational temperature that it fails final system test. If passivecomponents were integrated on a buried layer in the microelectronicsystem, where they could not be accessed and replaced, the entire valuework product value of the fully assembled system would have to bescrapped when it fails final test. Financial losses from the knownfailure rates that would be generated by embedding ceramic passivecomponents processed from powder precursors on a buried microelectroniclayer is sufficiently high that the number of fully assembled systemsthat could no longer be reworked and scrapped would eat up sufficienteconomic value to make microelectronic systems unaffordable forcommercial distribution at a profit.

A tighter performance standard, defined as critical performancetolerances, is required to reliably embed passive circuitry on a buriedmicroelectronic and eliminate subsequent rework risks. Consequently,semiconductor die having intrinsic clock speeds that run at ≥20 GHz mustlower their operational clock speeds down to 2.5 GHz to 3.4 GHz whenmounted on a printed circuit board. The higher signal frequencies neededto shape the digital pulse are distorted slow dielectric polarizationresponse times of the materials incorporated within the printed circuitboard and the passive components mounted upon it. Therefore, it isdesirable to improve computational speeds by displacing PCBs frommicroelectronic assemblies by means of integrating passive circuitelements that satisfy critical performance tolerances on the surface ofsemiconductor die that can be assembled in chip stack with profitableproductive yields. A preferred embodiment of the application utilizesdielectrics in the passive circuitry wherein capacitive dielectricelements have high energy density and maintain a paraelectric phase,which means the internal polarization of the dielectric is solelygenerated by orbital deformations and polarize in the presence of anddepolarize in the absence of an external electric field on femto-secondtime scales. Systems constructed with these means will not distort thehigher frequency signal components shaping the high speed digital pulse,and, thus, optimally perform at the intrinsic clock speeds of thesemiconductor die forming the fully assembled circuit module.

de Rochemont '839 and de Rochemont and Kovacs '814, incorporated hereinby reference, disclose means to form passive circuit elements 10 thatcomprise electroceramic dielectric members 12 wherein the electroceramicdielectric members 12 that determine passive component performance holdpassive components performance values to a high precision that keepstheir performance within ±1% of design specifications over requiredoperating temperatures. These tight tolerances define the criticalperformance tolerances that a prerequisite to integrating passivecircuit elements at the wafer scale. This means further enables waferscale integration of these materials at temperatures that do not alterdiffusion of dopant profiles of active circuitry embedded within asemiconductor wafer. This means claim in de Rochemont '839 and deRochemont and Kovacs '814 further enable an arbitrarily large number ofatomic elements to be incorporated with the electroceramic dielectricmember 12 to produce electroceramic dielectric members 12 having highenergy density that simultaneously satisfy critical performancetolerances. High dielectric densities are defined as electroceramicdielectric members 12 that have a relative permittivity (ε_(R)) inexcess of ε_(R).=40, preferably in excess of ε_(R).=200, or have arelative permeability (μ_(R)) in excess of μ_(R).=10, preferably inexcess of μ_(R). =100.

The nanoscale microstructure of these capacitive dielectrics maintains aparaelectric phase, wherein the polarization response is uniquelydetermined by orbital deformations. This allows electroceramicdielectric members 12 within capacitive passive components 10 to respondin phase to the presence or absence of an external field modulated up topetahertz (PHz), or 10¹⁸ cycles per second, signaling frequencies. Thesemeans enables the construction of embedded passive circuitry thatoperates without distortion well into the terahertz (THz) frequencydomain. Capacitive dielectric elements comprising nanoscalemicrostructures displace any need for printed circuit boards in any andall microelectronic assemblies, including hybrid computing modules. Itis therefore a desirable aspect of the present application to claimhybrid computing modules, servers, and server farms that do not comprisea single printed circuit board.

de Rochemont '385, incorporated herein by reference, instructs means toeliminate cache memory and effectively introduce minimal instruction setcomputing by means of a FORTH engine. FORTH engines have a processingarchitecture based upon the FORTH computer language that utilizesminimal instructions sets and greatly reduces the complexity with astreamlined interface that uses separate buses to access memory holdingthe data stack, return stack, a register, and the program memory. Thisfeature allows a FORTH engine to access all of these memory spacessimultaneously in a single microprocessor clock cycle. FORTH engines,also known as 2^(nd)-Generation Stack Processors, introduce remarkablepower efficiencies that enable these processors to cut processortransistor counts 1,000-fold while processing 2,300 MIPS (millioninstructions per second).

The use of a power management device 6 comprising a resonant gatetransistor 8 that eliminates a need for cache memory enables the greatpower efficiencies of FORTH engines to be repurposed to general usecases because a processor chip 106 mounted on the semiconductor carrier4 or embedded within the high-speed chip stack 2 can now directlyinteract with large dynamic memory sets with system interrupts as aFORTH engine. The 1,000-fold drop in transistor counts enabled by FORTHengines as a core processor chip 106 thereby reduce the powerconsumption of a network server 102 from 100s of Watts to 100s ofmilli-Watts or micro-Watts, depending upon the technology node used tomake the microprocessor.

de Rochemont '234, incorporated herein by reference, discloses means tointegrate passive circuitry within a high speed semiconductor chip stackthat enable the system clock speed of the chip stack to optimallyfunction at the intrinsic clock speed of the slowest clock speed of anysemiconductor die embedded within the chip stack. It is therefore apreferred embodiment of the invention to claim a server farm 100 orplurality of server farms 100, comprising servers 102 that furthercomprise hybrid computer modules 1 and high-speed chip stacks 2configured for minimal instruction set computing by means of a FORTHengine enabled by a power management device 6 that additionallycomprising a resonant gate transistor 8. These embodiments therebyenable the power consumption of a server farm 100 to be dropped fromMega-Watts per Hour (MW/Hr) down to Kilo-Watts per Hour (KW/Hr). Thisgreat savings in power consumption draws further distinction from theprior art through the use of hybrid computing module 1 or high speedchip stack 2 that optimally operate at the intrinsic clock speed of theslowest semiconductor die within the module 1 or stack 2 to boostprocessing speeds by roughly an order of magnitude or more.

Reference is now made to FIGS. 2A,2B,2C to illustrate a preferredembodiment of the application, which is a server farm 100 that comprisesa server 102, preferably a plurality of servers 102 inserted into slotsin a server rack 110, wherein the server racks 110 are stacked to form aserver tower 104, and the server towers 104 are a configured in rows 108of server towers 104, wherein the server or servers 102 further comprisea hybrid computing module 1 and the hybrid computing module 1 thatcomprises further still a high speed semiconductor chip stack 2. It isan additional embodiment of the invention for the hybrid computingmodule 1 to be configured for Minimal Instruction Set Computing by meansof a stack processor or FORTH engine as one of the semiconductor die 106embedded within or mounted upon the high speed semiconductor chip stack2.

A characteristic of the hybrid computing module 1, as instructed by deRochemont '385, is its ability to be tasked for general purposeapplications without a need for cache memory. This feature enables areturn to simpler information architectures, such as Stack MachineArchitectures. A microprocessor configured as a FORTH engine can process1,000s of MIPS (millions of instructions per second) while consumingmilli-Watts or micro-Watts (depending upon the technology node used tofabricate the semiconductor IC). A Stack Machine Architectures moreefficiently processes recursive and deeply nested loop algorithms withan efficiency that is 50% greater than iterative algorithms. Slackmachine processors are correspondingly less efficient (50%) inprocessing iterative algorithms, but that is an negligible drawback infavor of the prior art when the higher system clock speeds and enormouspower efficiencies are brought into consideration.

Cache memory and predictive algorithms were introduced as microprocessorclock speeds began surpassing the speed at which memory feed data andinstruction sets into the system. Cache memory systems usually operateon Last-in/First-Out (LIFO) and cannot independently access items in theprogram stack, so they only use iterative algorithms. This constraintdisplaced the efficiencies of true recursive and deeply nested loopalgorithms from computing information architectures, forcing tasksrequiring recursive or deeply nested loop calculations to be rewrittenas iterative algorithms. The linear rigidity of cache memory constraintsrequires sophisticated predictive algorithms to feed program stacks intothe microprocessor in accordance with what the predictive algorithmconcluded were the most probably strings of instruction sets and datathat will be needed to serve a general purpose environment.

Since predictive algorithms are not 100% accurate, cache memory swapsaccount for most of a microprocessor's power consumption. Since stackmachine information architectures require one program stack for operandsand a second program stack for operators, these simpler architecturesgot displaced as cache memory entered the market. It is therefore apreferred embodiment of the invention for the hybrid computing module tocall program stacks directly from main memory with little or no relianceon cache memory systems. It is an additional embodiment of the inventionfor the server farm 100 to comprise servers that manage some functionsusing stack machine architectures and further comprise a hybridcomputing module 1 that includes a high speed semiconductor chip stack2, which additionally comprises a semiconductor die 106 that operatesusing Stack Machine Architecture by means as a FORTH engine or anycomputer language or machine language that operates in a functionalcapacity similar to FORTH.

Memory storage is also another source for power losses in server farms.It is therefore desirable to develop means that mitigates power lossesderived from memory devices. X-Point (Cross Point) memory systems are anonvolatile semiconductor memory that uses a memory storage medium whoseresistance can be changed by an applied voltage rather than storingmemory bits as charge stored beneath an electrode that continuallyconsumes energy refreshing the stored charged state as is the case withdynamic random access memory (DRAM). An embodiment of the inventionclaims a hybrid computing module 1 or high-speed chip stack 2 thatcomprises at least one semiconductor die 106 that is an X-Point (CrossPoint) memory system or device 130 to eliminate power consumedrefreshing the charge states that form a bit and the energy expendedclocking the bits as charged states into cache memory. X-Point memorysystems or devices 130 read the data bit by reading the voltage dropacross the memory element (read voltage), making them far more powerefficient than other random-access memory systems. Another preferredembodiment of the application includes the use or a power managementdevice 6, preferably a power management device 6 that incorporates aresonant gate transistor 8 as a power switch, forms a bit pulse byreading the voltage located in one resistive element in one specificaddress location on the semiconductor die 6 that forms the X-Point(Cross Point) memory system 130. An additional preferred embodiment ofthe application includes the use of a power management device 6,preferably a power management device 6 that incorporates a resonant gatetransistor 8 as a power switch, wherein the power management device 6forms a plurality of bit pulses by reading the voltages located across aplurality or string of resistive elements across a plurality of memoryaddresses within a X-Point (Cross-Point) memory system 130 tosimultaneously form a plurality bit pulses as bit string during a singleprocessor clock cycle. It is a further embodiment of the applicationthat the bit string so constructed is interpreted either as word, orplurality of words. It is also desirable for these words to beindependently directed over a plurality of bus interfaces that include,but not limited to, a data stack bus, a return stack bus, a registerbus, a program memory bus, to allow the words simultaneous input/outputfrom a semiconductor (processor) die 106.

Furthermore, since a resistive element can comprise a plurality ofdifferent memory states, a single memory address can be used to store adata byte or word at a single memory address to increase memorydensities and reduce power consumption. It is therefore a preferredembodiment of this invention for the server farm 100 to comprise servers102, further comprising a hybrid computing module 1 or a high speedsemiconductor chip stack 2 that further includes a semiconductor die 106function as a nonvolatile X-Point (Cross Point) semiconductor memorysystem 130.

Individual servers 102 comprising hybrid computing modules 1 essentiallycomprise the volume of a modern circuit card. This size reduction allowsa plurality of servers 102 to be interfaced within a harness 109embedded within a server rack 110, wherein the server rack 110comprising a plurality of servers 102 occupies the volume of a slot in aconventional server rack, thus allowing a plurality of servers 102 to beinserted into the harness 110. The server racks 110 populated with aplurality individual servers 102 are inserted into rack slots within aserver tower 104. The server towers 104 are assembled into rows 108 ofserver towers 104. It is a preferred embodiment of the application thatharnesses 109 are designed to provide an optical interface between thehybrid computing modules 1 within a server 102, server rack 110, servertower 104, and rows 108 of server towers 104 within a server farm 100.Power management devices 6 and resonant gate transistors 8 may beembodied with the harness 100.

Reference is now made to FIGS. 2A, 3A, 3B, 3C, 3D, 3E, 3F, 3G toillustrate means to improve power management efficiencies whentransferring power from a primary electrical source 200, be it a highvoltage (≥600 VDC) battery or from the power grid 201. The power gridtransports AC electricity directly from the generating station 202through a generating set up transformer 204 that transforms the power topropagate long distances over transmission lines with minimal loss.Transmission line 206 voltages emanating from the generating set uptransformer range among 765 KVAC, 500 KVAC, 345 KVAC, 230 KVAC, or 138KVAC. Large power consuming applications, such as semiconductor tabs ordata centers/server farms, will draw power directly from thetransmission lines as a transmission customer 208, typically drawing inpower at 138 KVAC or 230 KVAC. Substation step down transformers 210 areused to directly supply sub-transmission customers 212 that draw powerat 26KVAC and 69KVAC. Primary customers 214 draw power at 13KVAC and4KVAC downstream from the sub-transmission customers 212. Secondarycustomers 216 primarily comprise family households and draw power at120VAC and 240VAC downstream from the primary customers 214.

Losses in delivering electric power from the power grid to the variousutility customers 208,210,214,216 are primarily derived from powermanagement stages that condition the power into a format (specificvoltage in an AC or DC mode) that is most useful to the customers208,210,214,216. Losses get compounded by having to pass the electricalpower through multiple power management stages. It is thereforedesirable to develop high efficiency power management stages 260 thatcondition power available directly from a power source 200. Powermanagement stages typically comprise a transformer stage that transformsan AC high voltage to an AC low voltage (step down) or transform an AClow voltage to an AC high voltage (step up). A power management stagemay also comprise an inverter stage the reconditions a DC voltage to ACvoltage (step up or step down). A power management stage may alsocomprise an inverter stage that converts an AC voltage to DC voltage tocharge a battery. The power management stage may also comprise one ormore converter stages that convert a DC voltage/current to a differentDC voltage/current (step up or step down). It is herein understood thata high efficiency power management stage 260 may perform any of thesefunctions but does so using 1-2 power management stages 260 when drawingelectrical power drawn any primary source 200 and conditioning to anyvoltage level AC or DC used within the server farm 100. Each highefficiency power management stage 260 is designed to have greater than95% power efficiency, preferably greater than 98% power efficiency,introducing substantial power loss reductions when extracting powerdirectly from the power grid 201.

Today, three (3) DC power management stages are needed to step down 120VAC or 600 VDC voltages drawn from a primary electrical source 200 downto the 1 VDC power levels that power semiconductor chips 106 in a server102. Modem high efficiency DC-DC power management stages operate with91%-93% conversion efficiencies. Multiple modem power management stagesare needed convert 120VDC to 1 VDC and will have an overall efficiencyof 75%-80%, losing 20%-25% of the power available at 120VAC or 600VDC.Higher losses are generated when transforming/inverting/convertingdirectly from the primary electrical source 200 through a significantlylonger string or power management stages.

An important aspect of the application is to minimize power losses in aserver farm 100 by minimizing the number of power management stages 260to 1-2 when managing the delivery of power from any primary electricalsource 200. The power management stage 260 comprises one or more highefficiency power management modules 218 and conditions the electricityavailable from a primary electrical source 200 to any of the voltages(AC or DC) consumed by the server farm 100. The reduction achieved inthe number of power management stages needed in a high efficiency powermanagement stage 260 is achieved by improving the power efficiency orminimizing power losses within every functional element used within inthe high efficiency power management module 218 and by maximizing thesustainable differential voltages across all the transformer coil 220windings 224 used within the power management stage 260.

Nearly all high efficiency power management modules 218 comprise atransformer coil 220, one or more power transistors, resistors, andcapacitors integrated into a single solid state body. Some DC-DCconverter and AC-DC converter topologies substitute the transformer codwith an inductor coil. Permeability (μ) is a measure of a material'sability to amplify magnetic flux densities in the presence of a magneticfield. Permeability (μ) is also inversely proportional to the magneticreluctance (

) of a magnetic circuit. Reluctance (

) is akin to electrical resistance in electrical circuits as magneticflux lines be directed around low permeability circuit elements. Just ashigh conductivity electrical conductors store very little electricalenergy internally within their bodies, high permeability magneticmaterials store little magnetic energy internally within their bodies.Similarly, just as electrical charge bypasseshigh-resistivity/low-conductivity conductive paths in favor orlow-resistivity/high-conductivity paths, magnetic flux lines deviatearound low permeability/high reluctance paths in favor of flowingthrough high permeability/low reluctance paths. Low permeability/highreluctance dielectric media stores more magnetic energy, just has lowconductivity/high resistivity dielectric media stores more electricalenergy.

A material's permeability (μ) is the product of the permeability of freespace (μ_(o)) and a material body's relative permeability (μ_(R)),(μ=μ_(o)μ_(R)). Higher magnetic flux densities are generated in materialbodies having higher relative permeability (μ_(R)). Magnetic fluxdensity (

) represents the strength of a magnetic current. The magnetic fluxdensity generated by a single ampere-turn (A/m) in a material bodyhaving μ_(R)=100 will be 100× greater than it is a non-magnetic materialbody having relative permeability μ_(R)=1. Higher magnetic flux density,

, generates greater self-inductance (L) within the inductor coil ortransformer coils 220. Inductance, L, is measured in Henrys orJoules-Ampere-⁻² (J/A²) or Weber-Ampere-⁻¹ (Wb/A), wherein a Weber isthe density of magnetic flux within an area of 1 square meter (m²)needed to generate 1 Tesla (T) from a unit of magnetic field strength,

measured as a the magnetic field generated when single ampere (A)circulating over a turn having a path length of 1 meter (A-m⁻¹).

Therefore it is desirable element of the application for magneticcomponents within a power management stage 260 to comprise magnetic corematerials 222 that have maximal permeability (μ) to transform, invert,convert maximal energy (Joules) in a single power management stage 260per unit of current (Amperes) input to the stage. Higher magnetic fluxdensities, and higher magnetic currents, within the magnetic core 222 ofan inductor coil or transformer coil 220 generate higher inductancesthat reduce the physical size of the inductor coil or transformer coils.Smaller component sizes reduce conductive losses within the highefficiency power management modules 218. A specific embodiment of theinvention claims magnetic core materials 222 that comprise a high energydensity electroceramic member 12 that has a relative permeabilityμ_(R)≥20, preferably a relative permeability μ_(R)≥100, most preferablya relative permeability μ_(R)≥400.

Primary loss mechanisms within any power management stage are magneticcore losses generated within inductor coils and transformer coils,proximity losses and flux jumping losses generated in inductor andtransformer coils. On-Resistance generated at the junctions of powertransistors, resistive losses generated in conductive elements andresistors, and dissipation losses generated in capacitors. Spuriousnoise created by electromagnetic interference (EMI) is also detrimentalto the operational efficiency of a power management stage. Therefore,means that minimize or neutralize all these loss mechanisms andoperational inefficiencies are necessary to from a high efficiency powermanagement module 218 and are desirable elements for improving the powerefficiency of server farms 100 claimed in this application, as well asall other power electronics used in electrical systems.

de Rochemont '708, incorporated herein by reference, instructs means toreduce power loss in magnetic core material 222 by embedding thin layers(≤1 μm) of amorphous silica 224 within the magnetic core 222 to killeddy current losses. Eddy currents are a major loss mechanism atswitching frequencies at UHF frequencies and above. Amorphous silica isthe most electromagnetically lossless industrial material and supportsthe highest dielectric breakdown voltage of all industrial materials. Itis therefore desirable for the high efficiency power management module218 to comprise a magnetic core material 222 that comprises embeddedamorphous silica layers 225 and high energy density electroceramicmembers 12. Since higher resistance magnetic materials generate smallerEddy currents, another preferred embodiment incorporates high energydensity electroceramic members 12 having electrical resistivity ≥10⁵Ω-cm, preferably greater than ≥10⁸ Ω-cm.

Preferred high energy density electroceramic members 12 within themagnetic core materials 222 comprise ferrite electroceramic whensubjected to modulating electromagnetic field frequencies less that 20MHz. Preferred high energy density electroceramic members 12 within themagnetic core materials 222 comprise hexa-ferrite electroceramic whensubjected to modulating electromagnetic field frequencies in the UHF/VHFfrequency bands. Preferred high energy density electroceramic members 12within the magnetic core materials 222 comprise garnets, preferablysilica garnets when subjected to modulating electromagnetic fieldfrequencies in excess of 1 GHz.

Higher resistivity magnetic core material 222 is another means ofreducing Eddy current loses. Higher resistivity is obtained when usingmagnetic materials comprising any of the following atomic elements:nickel (Ni), cobalt (Co), zinc (Zn), copper (Cu), titanium (Ti), andchromium (Cr). It is therefore a desirable aspect of the application forthe magnetic core material 222 within a high efficiency power managementstage 260 or an inductor coil or transformer coils 220 to comprise highenergy density electroceramic members 12 that further comprise, nickel(Ni), cobalt (Co), zinc (Zn), copper (Cu), titanium (Ti), and chromium(Cr).

Reducing hysteresis losses within the magnetic core material 222 isanother means of improving the efficiency of inductor coil andtransformer coils 220 within a power management stage 260. Lowerhysteresis loss is obtained when using magnetic materials comprising anyof the following elements: lead (Pb), strontium (Sr), and magnesium(Mg). It is therefore a desirable aspect of the application for themagnetic core material 222 within a high efficiency power managementstage 260 or an inductor coil or transformer coils 220 to comprise highenergy density electroceramic members 12 that further comprise: lead(Pb), strontium (Sr), and magnesium (Mg).

de Rochemont '708 instructs means to instill uniform electroceramicgrain size that optimizes magnetic permeability while minimizingmagnetic flux residual losses within the high energy densityelectroceramic member 12 of a magnetic core material 222. Residual lossis the dominant loss mechanism in magnetic core materials 222 atmodulation frequencies above 20 MHz. It is therefore desirable for thehigh efficiency power management module 218 to comprise a magnetic corematerial 222 that comprises high energy density electroceramic member12, preferably a silicon garnet electroceramic that maintains highmagnetic permeability (μ_(R)) above 1 GHz switching speeds, with amicrostructure having uniform grain size distribution size not greaterthan 7 μm in diameter, preferably uniform grain size distribution havinguniform grain size diameter in the range of 5-7 μm.

de Rochemont 708 also instructs means to encapsulate coil windings 224with enveloping amorphous silica dielectric 226 to enable transformersand inductors that sustain very large differential voltage drops,including 100s of KV differential voltages, between coil windings 224without generating electrical arcing between coil windings 224 in theinductor coil or transformer coils 220. It is therefore desirable forthe high efficiency power management stage 260 to comprise an inductorcoil or transformer coils 220 wherein the coil windings 224 areencapsulated with an enveloping amorphous silica dielectric 226.

de Rochemont 708 instructs means that impart coil windings with highhardness constraining members 228 are located at the center of a coilwinding 224. High hardness constraining members 228 are enveloped by lowresistivity conducting elements 230 having resistivity less than 10⁻⁵Ω-cm, preferably with resistivity less than 10⁻⁷ Ω-cm. Low resistivityconducting elements 230 typically have high coefficients of thermalexpansion (CTE≥17 ppm/° C.) that do not match well with amorphoussilica's CTE of 0.5 ppm/° C. The CTE mismatch and brittleness ofamorphous silica creates internal mechanical stress that crack theenveloping amorphous silica 226 when the transformer coil 220 isthermally cycled. High hardness constraining members 228 having tensilestrength greater than 1 GPa and CTE values less than 2 ppm/° C.,preferably a CTE value of 0.5 ppm/° C. that matches the CTE of amorphoussilica, relieve any thermally induced stress on the enveloping amorphoussilica dielectric 226 and the magnetic core material 222 because theexpansion of the malleable conducting elements 230 is constrained.

The inductor coil or transformer coils 220 remain in greater mechanicalbalance as it is thermally cycled with most of the mechanical stress andstrain located in the high hardness constraining members 228. It istherefore a preferred embodiment of the application for the highefficiency power management module 218 to comprise high hardnessconstraining members 228 within the cod windings 224. The high hardnessconstraining members 228 are selected to have thermal coefficients ofexpansion that optimally match the thermal coefficients of expansion ofthe enveloping amorphous silica dielectric 226 and the magnetic corematerial 222. Magnetic core material 222 is mechanically constrainedinternally by embedded amorphous silica layers 225 and externally by theenveloping amorphous silica dielectric 226. A further preferredembodiment of the application is a power management module 218 whereinthe high hardness constraining members 228 comprise low CTE ceramicshaving CTE≈0.5 ppm/° C. or low CTE ceramics in layered combinations withMAX-phase carbide ceramics as thermal management elements within thewindings to facilitate waste heat management, preferably through athermoelectric device 280, more preferably through a thermoelectricdevice 280 comprising a 3D quantum gas as instructed in de Rochemont'302/

de Rochemont 708 instructs means of forming toroidal inductor coils andtoroidal transformer coils 220 that minimize spurious signal noisegenerated from EMI created by magnetic currents that follow an opencurrent path. Magnetic currents within toroidal coil structures (asdepicted in FIG. 3B) follow a closed magnetic path, wherein the magneticflux lines are contained completely within the body of the transformercoil 220. Closed magnetic current paths emit greatly reduce spuriousnoise and EMI. Therefore, a preferred embodiment of the application is ahigh efficiency power management stage 260 or high efficiency powermanagement module 218 that comprises an inductor coil or transformercoils 224 further comprising toroidal geometry, wherein the magneticcurrents follow a closed magnetic path that terminates upon itselfcompletely within the coil structure.

A specific benefit of this application that was instructed by deRochemont 708 is the use of toroidal coil windings 224 that minimizeproximity losses and flux jumping losses by maintaining consistentphysical spacing between the coil windings 224 around the inductor ortransformer coil 220. It is therefore a preferred embodiment of theapplication for a high efficiency power management stage 260 or a highefficiency power management module 218 to comprise toroidal inductorcoils and transformer coils 220 wherein the toroidal inductor coil andtransformer windings 224 maintain consistent spacing between one anotherto reduce flux jumping and proximity losses.

de Rochemont 708 instructs means of forming a toroidal transformer coil220 that interleaves parallel coil windings with series coil windings toeffectuate step up/step down voltage transformations within a toroidaltransformer 220. These toroidal transformers 220 generate less parasiticnoise and higher coupling efficiencies, it is therefore a preferredembodiment of the application for a high efficiency power managementstage 260 or high efficiency power management module 218 to includetoroidal transformers coils 220 with interleaved primary and secondarywindings 224 are used to reduce parasitic noise and effectuatetransformer turn ratios.

FIG. 3B illustrates a 20:1 step-up transformer configuration wherein thesecondary coil 236 comprises 40 coil windings 224 in parallelconfiguration and the primary coil 238 comprises a single primary coilwinding 232. In this instance, all parallel configurations compriseparallel groupings 240 of two winding coils 224 configured in series,wherein each parallel grouping makes its parallel connection to a ringconductor 242 at points B. The parallel grouping of two winding coils224 configured in series evenly distributes the secondary currentreduces the effective turn ratio N_(p)/N_(s) by 2. A 20:1 step-downtransformer configuration would switch secondary coil windings 234 forthe primary coil windings 232 within the transformer 210 structure. Itis an additional preferred embodiment is a high efficiency powermanagement stage 260 or high efficiency power management 218 thatcomprises a toroidal inductor coil or transformer coils 220 that furthercomprise parallel groupings 240 of more than one winding coil 224configured in series, wherein each parallel grouping makes its parallelconnection to a ring conductor 242 tracing an arcuate path around thetoroidal coil.

A desired benefit of the application is to form magnetic core materials222 that reduce magnetic saturation and optimally store magnetic energywithin a magnetic circuit generally, and specifically when the magneticcore material is part of a power management module 218. Magneticsaturation is the over excitation of the magnetic core material 222 whenthe magnetic field strength, H measured in amperes per meter (A-m⁻¹)generates a maximal flux density, (

measured in Tesla (T). As depicted by curve 245 in FIG. 3C, at magneticsaturation 246 the generation of higher magnetic field strengths

created by higher currents circulating within a coil ceases to inducehigher magnetic flux densities

Magnetic saturation disrupts the linearity between input currents andcurtails a linear response of the self-inductances (L) that transfer orstore magnetic energy.

Another desired benefit is to mitigate abrupt transitions to magneticsaturation and maximizing energizing currents within an inductor coil ortransformer coils 220. Yet another desired benefit is to increasemagnetic energy coupling efficiencies between the magnetic core materialand the secondary windings 234 within transformer coils 220 used inflyback transformers or an inductor coil 220 used for energy storage orpower transfer.

These benefits are achieved by means of introducing one or more “airgaps” in conventional inductor and transformer coil structures. Higherenergies and higher magnetic field strengths

are created by within inductor or transformer coils 220 by introducingdielectric discontinuities wherein low permeability/high reluctancemedia (like air) are inserted within magnetic core material 222. Thefractional volume of low permeability media within magnetic corematerials 222 lowers the effective permeability of the core materials220 thereby allowing higher driving currents that impart greatermagnetic field strengths and magnetic energy within the inductor ortransformer coils 220 before the onset of magnetic saturation. Lowereffective permeability of a magnetic core caused by “air gaps” allowshigher electrical currents to energize the coils before the onset ofmagnetic saturation as shown in curve 247.

Energy generation benefits of the application include generating maximalmagnetic flux densities at optimal locations used to drive the creationof magnetic flux within an inductor or transformer coils 220 andcomprise any winding of (in the case of energy storing) an inductor coil220 and the primary windings 232 of transformer coils wherein themagnetic core material 222 beneath the aforementioned windings compriseshigh relative permeability (μ_(R)) in high energy density electroceramicmembers 12. The maximal positioning of high energy densityelectroceramic members 12 facilitates the generation of high magneticflux densities that optimizes the self inductance of a coil anddirectional flow of strong magnetic currents within an inductor coil ortransformer coils 220. Therefore, a desired aspect of the applicationmaximizes magnetic flux generation within an inductor coil ortransformer coils 220 by inserting a maximal volume of high energydensity electroceramic members 12 beneath one or more windings 224 of aninductor coil 220 and beneath one more primary coil windings 232 withintransformer coils 220. Maximal volumes for the occupied volume of highenergy density electroceramic members 12 comprises the volume spanned bythe cross-sectional area of the magnetic core material 222 and thelongitudinal length 248 of the magnetic core material between dielectricdiscontinuities 231,235.

Although necessary for generating high flux density (

) and high self-inductance (L) within an inductor coil or transformercoils 220, high relative permeability (μ_(R)) bodies limit magneticenergy stored in the coils' magnetic core material 222. Means tooptimize energy storage within an inductor coil or transformer coils 220used in switched mode power supplies is desirable to improving theefficiency transferred power within a high efficiency power managementstage 260.

Dielectric discontinuities in a magnetic core material 222 created byintroducing air gaps or nonmagnetic dielectric elements into the body ofthe magnetic core material 222 store significant amounts of magneticenergy due to their lower relative permeability (μ_(R)) and higherreluctance (

). It is not possible, or at least very challenging, to introduce airgaps within a solid state device. The optimal alternative createsdielectric discontinuities by inserting a continuous volume of ultra-lowloss amorphous silica dielectric 231 or a collection of small volumedistributed amorphous silica dielectric members 233.

Amorphous silica is functionally superior to air when substituted into adielectric discontinuity because amorphous silica dielectric members 231are non-magnetic (μ_(R)=1, like air), have loss tangent (tan δ) as lowas tan δ˜10⁻⁵, (like free space), and can sustain extremely highdielectric breakdown voltages (up to 10,000 KiloVolts-cm⁻¹). Theseperformance values are not possible using air as a dielectricdiscontinuity.

Therefore, a preferred embodiment of the invention claims a server farm100 comprising high efficiency power management modules 218 and highefficiency power management stages 260 that further comprise energystoring inductor or transformer coils 220 wherein the magnetic corematerials 222 comprise further still amorphous silica dielectric 231 ora collection of small distributed volumes of amorphous silica dielectric233 that are optimally positioned within the magnetic core material 222immediately beneath one or more windings 224 of an inductor coil 220designed for maximal energy storage or beneath one or more secondarycoil windings 234 of a transformer coil 220 designed for maximal powertransfer or for use as a flyback transformer in a switched mode powersupply of a high efficiency power management module 218.

Optimal energy storage locations 249A,249B within the magnetic corematerial 222 of transformer coils 221) are in close or immediateproximity to the transformer's secondary coil windings 234 or at selectwindings 224 specified by design objectives for an energy storinginductor coil 222. Optimal magnetic energy storage locations 249A,249Bcomprise high energy density electroceramic members 12 having magneticpermeability (μ), with relative permeability ≥20, preferably ≥400, andamorphous silica dielectric discontinuities 250,252. The volume ofoptimal magnetic energy storage locations 249A,249B comprises the volumespanned by the cross-sectional area of the magnetic core material 222mapped within the winding 224 under which it is located and 1.2× thelongitudinal length of the magnetic core material 222 that representsthe width of said winding 224. Alternatively the volume of optimalmagnetic energy storage locations 249B may comprise the volume spannedby the cross-sectional area of the magnetic core material 222 mappedwithin the winding 224 under which it is located and a longitudinallength 249B of the magnetic core material 222 that is less than or equalto the width 252 of said winding 224.

Optimally high currents passing through the winding of an inductor ortransformer coils 220 will generate lines of magnetic Held strength

within the ranges of linearity 253,255 defined in FIG. 3C. The generatedlines of magnetic field strength encircling around the closedlongitudinal path defined by the toroidal inductor coil and transformercoils 220 will spread out with uniform density across thecross-sectional area of the magnetic core material 222.

The magnetic flux density

generated by the lines of magnetic field strength

will be dominated by the relative permeability (μ_(R)) of the highenergy density electroceramic members 12 since they constitute themajority of the fractional volume within the magnetic core material 222that determines effective permeability (μ_(REff)) of the inductor andtransformer coils 220. Every line of magnetic field strength

within the coils will generate a magnetic flux density

=μ_(REff)×

that distributes itself uniformly across the high energy densityelectroceramic members 12. However, within optimal magnetic energystorage locations 249A,249B the nonmagnetic amorphous silica dielectricdiscontinuities 250,252 will reduce magnetomagnetic forces (MMF) withintheir bodies and store magnetic energy by pushing magnetic flux linesinto localized micro-volumes of extreme magnetic flux density 254,256where the deviating lines of magnetic flux will concentrate. Optimallythe dielectric discontinuities comprise a three-dimensional patternedarray that stabilizes these volumes of extreme magnetic flux density254,256 to induce maximal inductive coupling within the adjacentwindings 224,235. This higher inductive coupling releases the magneticenergy stored within magnetic energy storage locations 249A,249B whenthe inductor coils and transformer coils 220 are reverse cycled and thevolumes of extreme magnetic flux density snap back to a uniform densitydistribution. Spacing between the micro-volumes of extreme magnetic fluxdensity should range between 1/10,000th the volume of the magnetic corematerial beneath the secondary winding to 1/10th that volume.

It is therefore a preferred embodiment of the application topreferentially locate magnetic energy storage locations 249A,249Bembedded within the magnetic core materials 222 of an inductor coil ortransformer coils 220 to produce localized volumes of extreme magneticflux density 254,256 in immediate proximity to select windings 224 of anenergy storing inductor coil and one or more secondary coil windings 234within a flyback transformer, wherein the optimal magnetic energystorage locations comprise high energy density electro ceramic members12 having magnetic permeability (μ), with relative permeabilityμ_(R)≥20, preferably μ_(R)≥400, and amorphous silica dielectricdiscontinuities 250,252.

It is an additional preferred embodiment of the application tor thevolume of optimal magnetic energy storage locations 249A,249B tocomprise the volume spanned by the cross-sectional area of the magneticcore material 222 mapped within the winding 224 under which it islocated and 1.2× the longitudinal length 251 of the magnetic corematerial 222 that represents the width of said winding 224.

In another additional preferred embodiment of the application for theoptimal magnetic energy storage locations 249B to comprise a volumespanned by the cross-sectional area of the magnetic core material 222mapped within the winding 224 under which it is located and alongitudinal length of the magnetic core material 222 that is less thanor equal to the width 252 of said winding 224.

Dielectric discontinuities 231,233,250,252 have relative permeabilityμ_(R)=1 and operate to keep magnetic flux densities

=

. The deviating lines of flux expelled from amorphous silica dielectricdiscontinuities 231,233,250,252 induce fringing fields that cangenerated Eddy current loses with windings 224. Toroidal inductor coilsand transformer coils 220 form closed magnetic currents, which providemeans to reduce spurious noise by minimizing Eddy current losses withinthe conductive elements 228 of windings 224. Toroidal coil geometriesare that desirable feature of high efficiency power management modules218 and high efficiency power management stages 260.

Another preferred embodiment of the application inserts an envelopinglayer of nonmagnetic material 257 having μ_(R)=1 and preferablycomprises amorphous silica dielectric and has sufficient thickness toredirect fringing lines of magnetic flux back into regions of themagnetic core material 222 comprising a high energy densityelectroceramic member 12.

It is herein understood that high dielectric density electroceramicmembers 12 comprising localized volumes of extreme magnetic flux density254,256 are preferentially placed around all three dimensional bordersof amorphous silica dielectric discontinuities 231,233,250,252 and saidlocalized volumes are sufficiently large to minimize fringing fieldspenetrating into the conductive elements 228 of a winding 224.

de Rochemont '192 and '054, incorporated herein by reference, instructart related to a Resonant Gate Transistor 258 that allows large currentsto be switched at arbitrarily high speeds with minimal heat generationand power loss. A resonant gate transistor 258 embeds resonatinginductance within a transistor gate having elongated gate width(W_(gate)) and very short gate length (L_(gate)). The resonating gateinductance offsets the characteristic low frequency pass band imposed bythe gate's large capacitance, thereby enabling large currents to beswitched or modulated at high resonant frequencies with negligibleOn-Resistance at the transistor junction to minimize power loss and heatgeneration. In addition to greatly reduced transistor losses when switchlarge currents, system switching losses are also greatly reduced.

This near loss-less high-frequency current modulation allows largetime-averaged currents to be passed through the power switch at higherspeeds in smaller current packets ΔI. Each current packet ΔI injects anabrupt current spike that linearly decays to zero. Power switchinglosses are determined by:

P _(Loss)=(ΔI)²R   (1)

where R is the resistance in the system,

Large currents are typically switched at speeds of 10 MHz throughtransistors that generate massive heat and have high junction losses dueto their large On-Resistance. The resonant gates transistor's ability toswitch at speeds of 10 GHz reduces ΔI 1,000-fold to achieve the sametime-averaged current flow. Power switching loss, P_(Loss), is therebyreduced a million told.

A preferred embodiment of the application claims high efficiency powermanagement module 218 and high efficiency power management stage 260comprising a resonant gate transistor 258 as a power switch or as anelement within a fully integrated gyrator 300, an inductor coil ortransformer coils 220, preferably toroidal inductor coil or transformercoils 220, comprising high energy density electroceramic dielectricmembers 12 within the magnetic core materials 222 optionally comprisingoptimal energy storage locations 249A,24915, windings 224 comprisinghigh hardness constraining members 228, and enveloping amorphous silicadielectric 226 having sufficient thickness to electrically insulate aninductor coil or transformer coils 220 from arc discharges when theapplied differential voltage drops between their windings 224 exceed600VAC, preferably exceed 1 KVAC, more preferably exceed 50 KVAC, andeven more preferably exceed 250 KVAC. The high efficiency powermanagement stage 200 may be designed to serve all power managementconfigurations: AC-AC, AC-DC, DC-AC, and DC-DC to step up or step downthe output voltages. FIG. 3F depicts a high efficiency power managementexternal input stage 260A designed to step-down an AC voltage from aprimary electrical source 200 to an AC or DC voltage useful to supplyingthe server farm 100. A high efficiency power management external inputstage 260A comprises an input power block 261, one or more highefficiency power management modules 218, an internal power bus 276, andmay optionally comprise an energy storage facility 278 that may furthercomprise a battery, a flywheel, a resonant high energy storage device,or other means to store electrical energy.

The high efficiency power management external input stage 260A furthercomprises a current limiter circuit 272 that preferably comprises afully integrated gyrator 300 described in greater detail below. Thecurrent limiter circuit 272 interfaces with one or more power controlsystems 264 that regulate the flow of electrical currents into a lowloss AC-AC transformer stage 262 by monitoring input currents 268entering one or more high efficiency power management modules 218. Whena plurality of high efficiency power management modules 218 are requiredto effectuate the desired design objectives, the input currents areconfigured in parallel electrical connection as depicted in FIG. 3F.

The power control systems 264 preferably comprise one or more resonantgate transistors 258 designed to switch power at speeds in excess,preferably at switching speeds that are greater than or equal to 10× theswitching speeds of resonant gate transistors 258 incorporated withinthe one or more high efficiency power management modules 218. The powercontrol systems 264 may also comprise one or more fully integratedgyrators 300.

The one or more resonant gate transistors 258 comprising the powercontrol systems 264 electrically interface with a ladder circuit 282that rapidly monitors changes to the input currents 268 through currentsensors 270. The ladder circuit within power control systems 264attenuates currents flowing out of the current limiter circuit 272 tothe AC-AC transformer stage 262 before they rise to a level that willdamage the high efficiency power management modules 218 or electronicequipment housed within the server farm 100. The current limiter circuit272 comprises one or more resonant gate transistors 258 that aresynchronized with the resonant gate transistors 258 functioning withinthe power control systems and rapidly switches excess power emanatingfrom the primary electrical source 200 to ground when the ladder circuit282 senses a leading edge of pulse or power spike that exceeds specifiedlimits.

Parallel output currents 274 (AC or DC) from the high efficiency powermanagement modules 218 to an internal power bus 276 that supplies coreinternal power to the server farm 100 or general facility. The highefficiency power management modules 218 and the input power block 261may optionally form a thermal interface with a thermoelectric device280, preferably a thermoelectric device comprising a 3D quantum gas.

The high efficiency power management modules 218 within a highefficiency power management external input stage 260A may be designed tofunction as step down AC-DC inverters or ideal AC-AC transformers whenthe primary electrical source 200 draws electrical power from elementsof the power grid 201 serving transmission line 208, substation 212, andprimary customers 214, collectively referred to hereinafter as any otherfacility that consumes electrical power 204. The high efficiency powermanagement modules 218 within a high efficiency power managementexternal input stage 260A may be designed to function as a step up AC-DCinverter or ideal AC-AC transformer when the primary electrical source200 draws electrical power from the secondary customer 216 power linesof the power grid 201.

It is a specific objective of the application that all high efficiencypower management modules 218 within a high efficiency power managementexternal input stage 260A are designed to spurious signals that modulatephase and amplitude swings that are passed on to the power grid byswitched mode power supplies in DC-AC or AC-DC invertors and DC-DCconvertors that operate at non-optimal frequencies that are harmful tohuman health and is otherwise known as Dirty Electricity. This healthproblem is resolved by tuning resonant gate transistors 258 within highefficiency power management modules 218 designed to operate as filteringAC-AC transformers, wherein the resonant gate transistors 258 switchpower at optimal frequencies that are not harmful to human health andfilter Dirty Electricity from AC output voltages.

A preferred embodiment of the application comprises a high efficiencypower management external input stage 260A is designed to step-down anAC voltage from a primary electrical source 200 that comprise power gridvoltages serving transmission line customers 208, sub-stationtransmission line customers 212, or primary customers 214 wherein theinput power block 261 and the high efficiency power management modules218 are designed to step-down the output power as an AC or DC voltage.

An additional preferred embodiment of the application comprises a highefficiency power management external input stage 260A designed tostep-up an AC voltage from a primary electrical source 200 that comprisepower grid 201 voltages that serve secondary customers.

FIG. 3G depicts a high efficiency power management internal input stage260B designed to step-down a DC voltage drawn from a power bus 276internal to the server farm 100 or customer facility or a primaryelectrical source 200 that comprises DC voltage, such as 600 VDC, 800VDC, or higher other battery voltage. In this instance, DC power 276,200is input to the power control system 264 of the high efficiency powermanagement internal input state 260B. The power control system 264comprises a current limiter 272, a resonant gate transistor 258, a fullyintegrated gyrator 300, and a ladder circuit 282, current sensors 270that monitor changes in the amplitude of input currents 268. The powercontrol system 264 may optionally comprise a thermoelectric device 280that preferably is a thermoelectric device 280 that comprises a 3Dquantum gas.

In the instance where the high efficiency power management internalinput stage 260B is designed to step-down a DC voltage drawn from apower bus 276 internal to the server farm 100 or customer facility, oris supplied power from a primary electrical source 200 that comprises aDC voltage source, the high efficiency power management modules 218comprise DC to DC converters 218A, 218B, 218C that feed DC power 288 toDC power buses 284A 284B 284C at various voltages 1VDC 284A , 5VDC 284B, and 12VDC 284C or any other DC voltage that has value to the serverfarm 100 or other facility.

In another instance where the high efficiency power management internalinput stage 260B is designed to step-down or step-up a DC voltage drawnfrom a power bus 276 internal to the server farm 100 or customerfacility, or is supplied power from a primary electrical source 200 thatcomprises a DC voltage source to a desired AC output power at various ACvoltages, the high efficiency power management modules 218 comprise DCto AC inverters 218D, 218E, 218F that feed a plurality of AC parallelcurrents 290 to AC power buses 286A,286B,286C at various voltages 110VAC286A, 220VAC 286B, and 408VAC 286C or any other AC voltage that hasvalue to the server farm 100 or other facility.

Alternatively, a single AC power bus (any of 286A,286B,286C, depicting286A in FIG. 3G) may be used to feed additional low-loss transformers292 that step up or step down the AC power to the other AC power buses(depicting 286B,286C in FIG. 3G). AC power buses 286A,286B,286C maycomprise low-loss hollow waveguide structures.

A specific objective of the invention is a power management system 295that delivers electrical power drawn from the power grid 201 to a serverfarm 100 or any other facility that consumes electrical power and usesthree (3) high power efficiency power management stages 260A,260B,preferably only uses two (2) high power efficiency power managementstages 260A,260B, between the power grid 201 and any internal AC or DCpower bus 276,284A,284B,284C,286A,286B,286C in a server farm 100 or anyother facility that consumes electrical power.

An additional specific objective of the application is a powermanagement system 295 that comprises three (3) power management stages260,260A,260B, preferably only two (2) power management stages260,260A,260B, to reduce power losses generated delivering power from aprimary electrical source 200 to any internal AC or DC power bus276,284A,284B,284C,2846,286B,286C in a server farm 100 to 10%,preferably 5%, by using power management stages 260 that have powerefficiencies greater than or equal to 95%, preferably greater than orequal to 98%.

Reference is now made to FIGS. 4A,4B,4C,4D,4E,4F,4G,4H,4I to illustratevarious embodiments relating to a fully integrated gyrator 300.

The gyrator 301 is a passive, linear, lossless two-port electricalnetwork element 324 that cross couples voltage V₁ on port 1 307 to thecurrent n on port 2 317 or the current i₁ on port 1 307 to the voltageV₂ on port 2 317. Instantaneous currents (i₁,i₂) and instantaneousvoltages (V₁,V₂) are related by:

V₂=R_(/1) V₁=−R_(/2)   (2)

where R is the gyration resistance of the gyrator 301. Circuit topologyis used to tune the gyration resistance R of a gyrator 301, which can bemade to range from 10s Ω through 100s of KΩ.

The gyrator 301 is built with active transistors 302, operationalamplifiers (op-amps) 306 and feedback through one or more resistors 303,and one or more inductors 304 or capacitors 305. A gyrator 301 invertsthe current-voltage characteristics of an electrical current-voltagecharacteristic of an electrical component or network circuit. Withlinear elements, a gyrator 301 comprising a capacitor 305 will behavelike (simulate) an inductor 304, and when comprising an inductor 304 thegyrator 301 behave like a capacitor 305. Similarly, when the gyrator 302comprises a series LC network filter, it will perform like a parallel LCnetwork filter, and vice versa. A gyrator 301 that functions as asimulated inductor 320 comprises an op-amp 306, resistor 303, and acapacitor 304.

The simulated inductance and resistance of a gyrator 301 that functionsas a simulated inductor 320 are much greater than that of a physicalinductor and create inductive responses that range from the micro-Henry(μH) range up to the Mega-Henry (MH) range, whereas physical inductorsare limited to tens (10s) of Henrys (10 H). The parasitic seriesresistances of physical inductors range 100s of micro-Ohms (μΩ) tothrough to the low kilo-Ohms (KΩ). This wider dynamic rangetheoretically enables gyrators 301 that function as lossless idealtransformers 322 by cascading two gyrators 301 that function assimulated inductors 320 that creates voltage-to-voltage cross-couplingidentical to an ideal transformer 322. Gyrators 301 do not store anyenergy and cannot be used as a substitute in switched mode high voltagepower management systems 295 that require an energy storage inductorcoil or flyback transformer coils 220.

Existing gyrators 301 operate well below the theoretical potential ofthese ideal transformers 322. Key performance limitations forcontemporary gyrators 301 are limitations to the gain bandwidth oftransistor elements' 302 in the op-amp circuit 318, excess heatgenerated at higher switching speeds, and the tolerable power levels(voltage drops) that can be sustained by the transistor gate. Therefore,a desirable aspect of the present application is a fully integratedgyrator 300 that functions as an ideal, lossless transformer at highpower loads and with higher bandwidths. Methods and embodiments thatincrease transistor transition frequencies f_(T) (current gain bandwidthproducts) and improve power efficiencies are desirable to reaching idealtransformer performance using fully integrated gyrators 300.

Active transistors used in prior art op-amps 318 comprise standard fieldeffect transistors (FETs) or junction field effect transistors (JFETs).These transistors function effectively as a capacitor valve with a highfrequency cut-off that restricts higher bandwidth As noted above, theresonant gate transistor 258 instructed by de Rochemont '489/'532 embedsinductor elements (and other passive circuit elements) within thetransistor gate to cause it to resonant and switch large currents atfrequencies far higher than those achievable with the ubiquitouscapacitor topology prevalent throughout all the prior art.

The elongated transistor gate width instructed available throughresonant gate transistor 258 collect very large capacitance and arecapable of switching extremely large gain-enhancing currents at lowcurrent density and near negligible On-Resistance to further enhancegain beyond transistor transition frequencies f_(T) achievable withsimple capacitor filtering topologies. The introduction of additionalpassive elements within the transistor gate are used to transform thegate's frequency bandwidth from a simple capacitive filter with a highfrequency cut-off to that of a network filter that adds wider dynamicrange to improve gain-bandwidth product over a range of higherfrequencies than is possible with a simple FET or JFET. Furthermore, theability of the resonant gate transistor to embed highly resistiveelements between the gate and source electrodes permits the resonantgate transistor 258 to be which switched using large voltage drops,those removing the major constraints of modem op-amps.

It is therefore a specific embodiment of the invention to substitute atleast one transistor element 302, preferably all transistor elementswithin an op-amp circuit 318 with resonant gate transistor 258.

A gyrator 301 constructed under the prior all consists of a packagedop-amp 306 that has 8 pins (309, 310, 311, 312, 313, 314, 315, 316) tointerface the op-amp circuitry 318 with other circuit elements 303, 304or 305 mounted on a printed circuit board 326.

de Rochemont '234 instructs that commodity materials used to makesurface mounted passive components 303,304,305 and printed circuitboards 326 have a slow polarization response that distorts frequencycomponents and limit readable signals at frequencies above 2.5 GHz.

de Rochemont '234 further instructs means to fabricate high-speed chipstacks 2 and hybrid modules 1 that comprise passive circuit elements,further comprising high energy density electroceramic members 12 thatcan be integrated at the wafer scale to critical performance tolerances.

de Rochemont '234 additionally instructs that capacitors 305 laminatedat the wafer scale with high energy density electroceramic members 12having a uniform microstructure wherein all grains have uniformchemistry and uniform grain size less than 50 nm in diameter polarizeand depolarize at femto-second time scales and thus allow transistorclock speeds to be shifted from GHz frequencies into the THz domain.

de Rochemont '234 further instructs means to embed passive circuitry ator very near to the vias in high-speed chip semiconductor stacks tominimize stub lengths that impose an additional limitation on high speedcircuitry.

It is therefore a preferred embodiment of the application claims a follyintegrated gyrator 300, preferably a loss-less transformer 350 thoughany and all gyrator embodiments are similarly claimed, that comprises ahigh speed stack of semiconductors 352, that may be a stacked assemblyof semiconductor chips 354A or stacked assembly of semiconductor wafers356B, wherein one or more semiconductor chip 354A or wafer 356Acomprises transistor elements 302 needed to form an operationalamplifier circuit 318 and at least one of said transistor elements 302,preferably all of said transistor elements 302, is a resonant gatetransistor 258.

An additional preferred embodiment of the application claims a fullyintegrated gyrator 300, preferably a loss-less transformer 322 thoughany and all gyrator 300 embodiments are similarly claimed, thatcomprises a high speed stack of semiconductors 352, that may be stackedsemiconductor chip 354 or stacked semiconductor wafer embodiments 356,wherein one or more semiconductor interposer chips 354B or wafers 356Bcomprises all passive circuit elements 303,304,305 needed to form anoperational amplifier circuit 318 and those additional passive circuitelements 303,304,305 that are needed to form a fully integrated gyratorcircuit 300 are integrated as laminated components within thesemiconductor interposer chip 354B or wafer 356B.

Yet another embodiment claims a high speed stack of semiconductors 352,comprising one or more gyro tors 300 within the high speed stack ofsemiconductors 352 wherein vias electrically interface passive circuitelements 303,304,305 laminated on and integrated within a semiconductorinterposer chip 354B or wafer 356B through a bonded internal majorsurface interface 360 that mates with transistor elements 302 needed toform an operational amplifier circuit 318, wherein and at least one ofsaid transistor elements 302, preferably all of said transistor elements302, is a resonant gate transistor 258, in the semiconductor chip 354Aor semiconductor wafer 356A.

Another embodiment claims a fully integrated gyrator 300 comprising ahigh speed stack of semiconductors 352 wherein the input/outputelectrodes 362A are located on one major exterior surface 363 of thestack of semiconductors 325A and the output/input electrode 362B of thestack of semiconductors 325 opposing major surface 364.

Yet another embodiment claims a cascading stack 366 of fully integratedgyrators 300, wherein the output electrode 362B on the major surface ofthe first gyrator 300A is bonded to the input electrode 362A on themajor surface of the second gyrator 300B.

Another embodiment claims a cascading stack 366 of fully integratedgyrators 300 that further comprises a plurality of cascading stacks 366of fully integrated gyrators 300.

Yet another embodiment claims a cascading stack 366 of fully integratedgyrators 300 that operates as a loss-less transformer 322.

Another embodiment claims a fully integrated gyrator 300 that inverts anetwork filter 320.

Yet another embodiment claims a cascading stack 366 that comprises oneor more fully integrated gyrators 300 that operate in tandem astransformers 322 and network filters 320 and together form a complexcircuit.

Yet another embodiment claims a fully integrated gyrator 300 wherein thepassive circuit elements 303,304,305 comprise high energy densityelectroceramic members 12 that satisfy critical performance tolerances.

Another embodiment claims a fully integrated gyrator 300 wherein aresonant gate transistor 258 comprises a high resistivity resistorelement, imparting resistance greater than 1 KΩ, preferably greater than1 MΩ, between the gate and source electrodes in high power switchingapplications.

Yet another embodiment claims a fully integrated gyrator 300 wherein aresonant gate transistor 258 comprises a plurality passive elements303,304,305 integrated within the gate electrode to induce resonanceover a wide frequency band or at particular frequency bands thatoptimize gain-bandwidth of the resonant gate transistor 258 for thefunction of the fully integrated gyrator 300 or cascading stack 366 offolly integrated gyrators 300. Another embodiment claims a fullyintegrated gyrator 300 wherein the laminated passive circuit elements303,304,305 that are laminated on and integrated within thesemiconductor interposer chip 354B or wafer 356B are located in close orimmediate proximity to a via.

An ideal loss-less transformer that, comprises a parallel array 370 ofcascading stacks 366 of folly integrated gyrators 300 configured inparallel.

Reference is now made to FIGS. 5A,5B to illustrate a regional serverfarm network 400 or a global network 402 comprising the server farms100. The regional server farm network 400 comprises a plurality ofserver farms 100 in digital or analog communication with each otherthrough wireless transmission links 404 or fiber optic transmissionlines 406, or through a combination of wireless transmission links 404and fiber optic transmission lines 406. A preferred embodiment of theregional server farm network 400 comprises microelectronic hardwarefunctioning as routing and relay systems at wireless network nodes 408and/or fiber optic network nodes 410 that comprises a hybrid computingmodule 1 and high speed semiconductor chip stacks 2 tor all taskscritical to accelerating transmission speeds between the server farms inthe regional network.

The higher gain-bandwidth available through the resonant gate transistoras discussed above in power switching also has utility in improvingtelecommunications. Therefore, a specific embodiment of the applicationclaims telecommunications network nodes 414 (wireless 408, satellite410, and optical 412) wherein the telecommunications hardware comprisesa resonant gate transistor 258, and signal modulation devices thatfurther comprise a high speed chip stack and capacitive passive elements10.

As referenced above, commodity materials used in printed circuit boardsand discrete passive circuit elements distort higher frequency signalpulses need to shape the high speed digital pulse. As instructed in deRochemont & Kovacs '814, electroceramic dielectric members 12 havingnanoscale microstructure maintain their precise performance stable withvarying temperatures and generate higher signal integrity, whichimproves telecommunications bandwidths at a telecommunications networknode 414.

de Rochemont '234 instructs that electroceramic members 12 havingnanoscale micros tincture enable broader signaling bandwidths becauseorbital deformation is the only charge displacement mechanismcontributing a polarization response from these materials and, thus,moves in phase with modulating signals down to femto-second (10⁻¹⁵ sec)time scales. Whereas, commodity materials used in prior artconstructions distort signal operating above 2.5 GHz-3.4 GHz.

Therefore, an additional embodiment of the application claimsmicroelectronic hardware and signal modulation systems attelecommunications network nodes that compromise electroceramic membersthat comprise capacitive dielectric material having nanoscalemicrostructure.

Improved power efficiency is another desirable element of theapplication. Therefore, telecommunications networks wherein the networknodes that comprise hybrid computing systems that further comprise aFORTH engine, resistive element X-(Cross-Point memory and use no cachememory are clear benefits of the application.

Another benefit of the application is reduced power management loss.V_(DD) modulators are often used to reduce DC power losses whenmodulating AC signal envelopes, but suffer the same higher frequencydistortions caused by commodity materials. Therefore, a desired benefitis a telecommunication comprises a V_(DD) modulator that furthercomprises a resonant gate transistor 258, toroidal inductor andtransformer coils 208, and electroceramic dielectric members 12 havingnanoscale microstructure to minimize phase distortions.

Additional benefits include power management systems comprising fullyintegrated gyrators functioning as lossless transformers.

The global server farm network 402 comprises a plurality of regionalserver farm networks 400 in digital communication with each otherthrough wireless transmission links 404 that will most often comprisesatellite wireless links 412, or fiber optic transmission lines 406,which most often will be transoceanic cables, or through a combinationof wireless transmission links 404 and fiber optic transmission lines406. A preferred embodiment of the global server farm network 402comprises microelectronic hardware functioning as routing and relaysystems at wireless network nodes 408 and/or fiber optic network nodes410 that comprises a hybrid computing module 1 and high speedsemiconductor chip stacks 2 for all tasks critical to acceleratingtransmission speeds between the server farms in the regional network.

1. A server farm comprising a server, wherein the server or serverscomprise: at least one hybrid computing module operating at a systemclock speed that optimally matches the intrinsic clock speed of asemiconductor die embedded within a high speed semiconductor chip stackor mounted upon the semiconductor carrier; and one or more high-speedsemiconductor chip stacks bonded to the surface of a semiconductorcarrier in which at least one passive component element, preferably allpassive components elements maintain critical performance tolerances,and have a polarization response time determined solely by orbitaldeformations and operates in phase, thus does not distort, any of theapplied signal components forming a high-speed digital pulse operatingat clock speeds up to and into the terahertz (THz) frequency domain. 2.A server farm as in claim 1, wherein the hybrid computing module withina server or plurality of servers comprises a power management devicethat further comprises a resonant gate transistor.
 3. The server farm ofclaim 2, wherein the hybrid computing module is configured for MinimalInstruction Set Computing by means of a chip that comprises a FORTHengine mounted on a semiconductor carrier or embedded within a highspeed chip stack.
 4. The server farm of claim 2, wherein the hybridcomputing module configured for Minimal Instruction Set Computingutilizes a computing language other than FORTH, but the processor chipthat enables the engine to adopt a Stack Machine Architecture hasfeatures similar to a FORTH engine including: the ability to accessmultiple memory spaces simultaneously in a single microprocessor clockcycle; and, that utilizes a minimal number of instruction sets throughthe use of separate buses to access memory holding the data stack, thereturn stack, and the program memory, among other useful programutilities.
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 9. Apower management system that delivers electrical power from the powergrid or a primary electrical source to a server farm or other facilitythat consumes electrical power and only requires three high efficiencypower management stages, preferably only requires two high efficiencypower management stages, between the power grid or primary power sourceand any internal AC or DC power bus in the server farm or any otherfacility that consumes electrical power.
 10. A power management systemas in claim 9, that has a power efficiency of 90% that reduces systemlosses to 10%, and preferably has a power efficiency of 95% that reducessystem losses to 5%, when delivering power from the power grid or from aprimary power source any internal AC or DC power bus in the server farmor any other facility that consumes electrical power.
 11. The powermanagement system of claim 9, wherein, the high efficiency powermanagement stage comprises an input power block that further comprises:one or more power control systems that regulates the flow of electricalpower from the power grid or a primary electrical source by means ofcurrent sensors and a current limiter that electrically isolate one ormore power management modules within the power management system, a lowloss transformer stage, and one or more high efficiency power managementmodules that interface AC power input from the power grid or a primaryelectrical power source to an AC or DC power bus internal to the serverfarm or other facility that consumes electrical power.
 12. The powermanagement system of claim 11, wherein the current limiter synchronouslyoperates with a resonant gate transistor interfaced with a laddercircuit that rapidly monitors changes to input currents being teed intopower management modules to detect power spikes or pulse edges that arecharacteristic of a power surge that will likely damage high efficiencypower management modules or equipment within the server form or otherfacility that consumes electrical power, and then uses a resonant gatetransistor within the current limiter to shut the power surge to ground.13. An inductor coil or transformer coils that form low loss inductorsand low loss transformers comprise magnetic core materials that havemaximal permeability and minimal magnetic core losses by furthercomprising high energy density electroceramic members that: minimizeEddy current losses by consisting of any one or all of the flowingatomic elements: nickel (Ni), cobalt (Co), zinc (Zn), copper (Cu)titanium (Ti), or chromium (Cr); minimize hysteresis losses byadditionally consisting of any one or all of the following atomicelements: lead (Pb), strontium (Sr) and magnesium (Mg); minimizeresidual magnetic loss by additionally having a microstructure with auniform grain size distribution not greater than 7 μm, preferably auniform grain size distribution in the range of 5-7 μm; and, furtherminimize Eddy current losses by embedding one or more thin amorphoussilica layers having thickness ≤1 μm.
 14. The magnetic core materials ofclaim 13, wherein high energy density electroceramic members haveelectrical resistivity ≥10⁵ Ω-cm, preferably ≥10⁷ Ω-cm.
 15. The inductorcoil or transformer coils of claim 13, wherein higher energies andhigher magnetic field strengths are created by introducing dielectricdiscontinuities by include nonmagnetic media within the magnetic corematerials to create “air gaps” that allow higher currents to energizethe inductor coil or transformer coils before the onset of magneticsaturation.
 16. The inductor coil or transformer coils of claim 15,wherein the inductor coil and transformer coils form a closed magneticpath by means of toroidal geometries that reduce parasitic noisegenerated by fringing fields and Eddy current losses generated byelectromagnetic interactions between magnetic fringing fields leakingout of the magnetic core material and currents in the coil windings. 17.(canceled)
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